Friends -
On Sat, Jun 02, 2007 at 09:08:22AM +0200, L.J.H. Timmerman wrote:
Or does a defacto standard format already exist ?
Together with a netlist of connecting traces this would give enough
information for testing conductity in an automated fashion.
Does IPC 356 do what you want? A shop
Ryan -
On Tue, May 15, 2007 at 09:22:51AM -0400, Ryan Seal wrote:
Is there a method in PCB that allows one to measure the trace length so
that signals can be phase matched if needed? If not, this would be a
nice feature.
No, but I would be interested to help out, either coding or
testing.
On Tue, May 01, 2007 at 08:01:48PM -0700, Matt Ettus wrote:
I get the following errors when trying to compile a dual-ported ram in
icarus. I'm sure my syntax must be bad somewhere, but I can't see
where.
I get different errors, which go away if I replace 2**ADDR_WIDTH
with 32.
- Larry
Svenn -
On Tue, Apr 10, 2007 at 05:54:19PM +0200, Svenn Are Bjerkem wrote:
A wire jump tells the reader _explicitely_ Here are two wires
crossing. [chop] When
they _are_ automagically generated, like in Visio, I tend to use them
as there are no questions like do those lines cross or are they
Svenn -
On Tue, Apr 10, 2007 at 06:32:31PM +0200, Svenn Are Bjerkem wrote:
A solder dot does _explicitely_ tell the reader that there is a
connection. The lack of a solder dot does not explicitely tell you
[chop]
If you want to tell people that they should use wire jumps in
their schematics,
On Tue, Apr 03, 2007 at 04:00:24PM -0400, DJ Delorie wrote:
I have enough problems with my word processor changing case when I
don't want it to, I certainly don't need my file system doing it too.
It recently took me five minutes to sweet-talk openoffice into
letting me type MHz correctly.
David -
On Tue, Apr 03, 2007 at 04:52:52PM -0400, David Kerber wrote:
There's a much shallower option to add [MHz] to the dictionary, so it will
even correct it next time...
Openoffice didn't just show it with a red squiggly underline,
it actively changed it as soon as I typed it. How could
On Sun, Mar 25, 2007 at 11:50:57AM -0400, Jeremy Pedersen wrote:
If it's the lesstif version, it's in the Tools menu. In the GTK
version, you can use the buttons on the left.
Ok. Is it the THRM button? If so, I can't get it to work. I click it, and it
gives me a small black symbol
Steve -
On Fri, Mar 16, 2007 at 10:39:28AM -0700, Stephen Williams wrote:
Are the Layers controls dialog box buttons connected to anything?
I try to move one of the existing layers out of the group that it
is in to a group of its own (I'm trying to create a ground plane)
but it doesn't stick.
On Sat, Mar 10, 2007 at 10:11:32PM -0500, [EMAIL PROTECTED] wrote:
Nested for loops don't seem to work in iverilog.
it would seem that only the inner loop is updated.
reg signed [7:0 ] x, y;
for (x = -128; x 128; x = x + 1)
Stop right there. x128 is _always_ true, since
On Sat, Mar 10, 2007 at 10:37:11PM -0500, [EMAIL PROTECTED] wrote:
Look more closely. What is the bit pattern for +128, in 8 bits?
What is the bit patters for -128 in 8 bits? And for extra credit,
what comes after 127 when counting in 8 bits (signed)?
Thank you very much for the response.
SImon -
On Thu, Mar 08, 2007 at 06:07:54AM +, ST de Feber wrote:
Are you sure it is icarus or the construct itself ?
Have you tried it with e.q modelsim ?
Well, that's what I hoped someone else on the list could
tell me. I don't have access to or experience with modelsim.
Steve Williams
Andy -
On Wed, Dec 13, 2006 at 11:15:12AM -0700, Andy Peters wrote:
Just to clarify: if I use GPLed or BSD-licensed tools to develop
hardware, as well as using GPLed symbols/footprints, am I obligated
to open-source the hardware design (the schematic, the PCB layout)?
If you never
On Wed, Dec 13, 2006 at 06:28:34PM +, Peter TB Brett wrote:
[a bunch of stuff pretty much aligned with what I wrote]
This is why either:
- IMHO footprints or symbols should be distributed under the GPL license
I take it you mean should _not_ be.
- Larry
Greg -
On Wed, Nov 08, 2006 at 12:42:06PM +1100, Greg Cunningham wrote:
What about shifting the bit-banging into a IRQ/timer-driven kernel
module that sends smoke signals (not literally...) to user-land when the
tx/rx sequence is complete? a bit like a software UART emulation...
You still
Friends -
On Mon, Nov 06, 2006 at 07:08:48PM -0500, DJ Delorie wrote:
DJ, Are you writing code for the Dallas 1-wire protocol? Neat.
Lots of bit banging.
If anyone wants FPGA code for 1-Wire, I have some. You can
either click through the stupid (but innocuous) licence
agreement at
Dave -
On Wed, Nov 01, 2006 at 09:12:49PM -0500, Dave McGuire wrote:
It all depends on what you're into. I've been discussing a
project with a friend that would involve building what amounts to a
copy of the PDP-8 (Straight-8, no suffix) with individual
transistors. It's fun, cool,
Michael -
On Tue, Oct 31, 2006 at 05:05:21AM +, Michael Sokolov wrote:
[EMAIL PROTECTED] wrote:
Ditto for the Xilinx toolchain on my box. [chop]
I've tried it, but got turned off in utter disgust when I saw that the
thing is packaged in encrypted (!) ZIPs specifically to make it
DJ -
On Thu, Sep 21, 2006 at 11:47:38AM -0400, DJ Delorie wrote:
I'm thinking I should design in some series resistors on the address
and data lines for my RAM expansion board (30MHz, about 6 of 8 mil
trace on DS FR4, 5v).
5 Volts? How quaint.
You didn't give the thickness of the FR4
DJ -
On Thu, Sep 21, 2006 at 12:18:46PM -0400, DJ Delorie wrote:
Double sided, 0.062.
How quaint. ;-)
The board I'm in the middle of bringing up is 6-layer, 0.045.
I've probably linked to it before:
http://recycle.lbl.gov/llrf4/
So the distance between a trace and its ground plane is
an
On Thu, Aug 24, 2006 at 11:16:19AM +0100, Hugo Elias wrote:
3. Instead of saying in the log copper areas too close. Why not say
something like via too close to track for example.
Or better still,
via too close to track on layer 3
- Larry
___
DJ -
On Mon, Aug 21, 2006 at 02:01:51PM -0400, DJ Delorie wrote:
Plus scattering some 10uF (also 0603 ceramic) around.
Or this one: digikey PCC2233CT-ND
10uF 0805 ceramic, 10v, +20% -80%, only $0.20 each.
Have you ever looked at the capacitance-vs-voltage
curves for Y5V dielectric? Yuck.
Patrick -
On Tue, Aug 15, 2006 at 03:51:41PM -0400, Patrick Doyle wrote:
The feature I'm most looking forward to coming out of this exercise is
the ability to back annotate pin-swap information. Right now I'm just
plugging my busses together between the processor and the memory (or
interface
On Thu, Jul 27, 2006 at 12:39:46PM -0400, Stuart Brorson wrote:
I'd do it with PostScript output straight from PCB, but I understand
that PostScript's 1:1 doesn't really mean 1:1 exactly. Or am I wrong?
There's always the chance your printer is badly calibrated.
Except for that, it's fine.
On Tue, Jul 25, 2006 at 11:52:59AM +0200, Stefan Salewski wrote:
I have the same problem, using geda shipped with gentoo-linux
(AMD64):
[EMAIL PROTECTED] ~ $ gerbv --version
gerbv version 1.0.1
(C) Stefan Petersen ([EMAIL PROTECTED])
Works fine for me -- same gerbv, also on AMD64.
I tried
On Wed, Jul 19, 2006 at 04:49:14PM -0400, DJ Delorie wrote:
How large a pcb layout can PCB handle?
About a quarter of a mile per side. Yes, I've done this, my house
looks *really* small on that scale.
Just for the fun of it, I just tried to set a huge board size.
I got bumped back to 30
On Wed, Jul 19, 2006 at 05:02:03PM -0400, DJ Delorie wrote:
Just for the fun of it, I just tried to set a huge board size.
I got bumped back to 30 inches on a side. This is from the
Preferences/Sizes GUI in CVS PCB-HID-gtk.
Try the lesstif HID. It doesn't have any of the arbitrary
On Wed, Jul 19, 2006 at 02:56:28PM -0700, Art Fore wrote:
We only need about 18 inches X 18 inches and up to 24 layers. How about
ground planes? Does it also handle split ground planes?
Heretic! Ground planes are by definition not split!
Fortunately for you, PCB is agnostic on the subject.
Tamas -
On Fri, Jul 14, 2006 at 11:31:24AM +0300, Tamas Varga wrote:
It works for me, too. Thanks.
2. Same problem as previous when dragging the designator
of a part placed on the solder size.
I guess bug 2 is something similar to this.
I didn't check it before, but bug 2 is not present on
Friends -
In PCB, I put down an exposed-paddle part (like the CY7C68013A-56LFXC),
and then put vias in the central region as recommended for both thermal
transfer and electrical connection. Just like the rest of the pad,
those vias are clear of solder mask.
According to the manufacturer's
DJ -
On Wed, Jul 12, 2006 at 06:45:05PM -0400, DJ Delorie wrote:
[EMAIL PROTECTED] writes:
Has anyone found (or put in) a method to [cover vias-in-pads with
solder mask] in PCB?
Thought - try using 12 thin pads instead of one big one, to build a
grid with the 25 vias in the gaps in the
31 matches
Mail list logo
