I recently found out (painfully) that an intuitive
and excellent feature of iverilog is nonstandard.
The OVI reference manual states:
The text specified for MACRO_TEXT must not be split across the
following lexical tokens:
* comments
* numbers
* strings
*
I've been having trouble with strengths.
I think there may be a bug, unless I'm
using them incorrectly.
Consider:
module test;
tri blah;
assign (pull1, strong0) blah = 0 ? 0 : 1;
assign blah = 0;
initial
$display(Blah should be 0:
On 30 Apr 2007, at 10:20:13 PM, Stephen Williams wrote:
I've looked at the thread in comp.lang.verilog. The parameter
definition circularity problem is nasty, but a carefully contained
extension (a la the way Modelsim handles it) seems plausible.
This is a good candidate for the Feature Request
On 1 May 2007, at 4:02:28 AM, Evan Lavelle wrote:
Stephen Williams wrote:
[EMAIL PROTECTED] wrote:
Basically, I'm whining for a feature.
I've looked at the thread in comp.lang.verilog. The parameter
definition circularity problem is nasty, but a carefully contained
extension (a la the way
Hello again.
I'm completely confused.
Please bear with me.
I have defined with the VPI a task
that computes the square root
of a real input to produce a
real output.
The task is called $FloatSqrt and it
is defined thusly:
static PLI_INT32 calltf_FloatSqrt(PLI_BYTE8* user)
{
On 7 Apr 2007, at 7:18:42 PM, [EMAIL PROTECTED] wrote:
Hello,
I had a bunch of parameters that I was duplicating across modules,
so I decided to replace them with macro definitions in one file.
After creating this file and including it in my other files, I kept
getting
these errors:
Hello again,
I've been playing around with $realtobits and $bitstoreal,
and I've found things aren't as clean as I'd hoped.
Basically, I want to simulate floating point operations in my modules.
I figured the process would be:
(1) Convert a real to bits and pass those as an input to a
On 7 Apr 2007, at 10:57:19 AM, Stephen Williams wrote:
*sigh* This is bad enough to be called a bug. If you have a small
example that triggers this aspect, can you file it as a bug report?
You have my permisison to nudge its priority up to 6 because this
is actually quite embarrassing:-(
Hello,
I had a bunch of parameters that I was duplicating across modules,
so I decided to replace them with macro definitions in one file.
After creating this file and including it in my other files, I kept
getting
these errors:
warning: macro `include undefined (and assumed
On 5 Apr 2007, at 11:22:18 AM, Stephen Williams wrote:
[EMAIL PROTECTED] wrote:
I've made a BMP image format creating module for fun.
I maintain a 640x480 24-bits per pixel buffer and then write the data
out to a file.
At first I used a reg array, but came to find that each element of
I've made a BMP image format creating module for fun.
I maintain a 640x480 24-bits per pixel buffer and then write the data
out to a file.
At first I used a reg array, but came to find that each element of
such a structure
is expressed in vvp assembly as distinct reg. This made the vvp
Nested for loops don't seem to work in iverilog.
it would seem that only the inner loop is updated.
Consider the following:
module TestMultiplier;
reg signed [7:0 ] x, y;
wire signed [15:0] z;
initial
begin
$dumpvars;
for (x = -128; x 128; x = x
On 10 Mar 2007, at 9:58:51 PM, [EMAIL PROTECTED] wrote:
Nested for loops don't seem to work in iverilog.
it would seem that only the inner loop is updated.
Consider the following:
module TestMultiplier;
reg signed [7:0 ] x, y;
wire signed [15:0] z;
initial
begin
On 10 Mar 2007, at 10:18:41 PM, [EMAIL PROTECTED] wrote:
On Sat, Mar 10, 2007 at 10:11:32PM -0500, [EMAIL PROTECTED]
wrote:
Nested for loops don't seem to work in iverilog.
it would seem that only the inner loop is updated.
reg signed [7:0 ] x, y;
for (x = -128; x 128; x = x
On 10 Mar 2007, at 10:29:47 PM, Stephen Williams wrote:
Look more closely. What is the bit pattern for +128, in 8 bits?
What is the bit patters for -128 in 8 bits? And for extra credit,
what comes after 127 when counting in 8 bits (signed)?
Thank you very much for the response.
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