andrewm wrote:
I like your minimization of vias. Most of your vias seem to double as
headers for test and interconnect. Looks good. Good use of space --
little waste, but not too crammed to be a practical test/eval/modular
add-on board.
John Griessen
PS What's it look like if you run
On Sat, Sep 15, 2007 at 12:51:36PM +1000, andrewm wrote:
http://www.thehacktory.com/IR-simple-v1p52-top.png
If that big square is a thermal pad, it's not going to help much if
you don't stitch it to more copper on the other side...
Also, I think your attachments to the sides of those long,
Ben Jackson wrote:
On Sat, Sep 15, 2007 at 12:51:36PM +1000, andrewm wrote:
http://www.thehacktory.com/IR-simple-v1p52-top.png
If that big square is a thermal pad, it's not going to help much if
you don't stitch it to more copper on the other side...
So, what is that under chip square of
John Griessen wrote:
I like your minimization of vias. Most of
your vias seem to double as headers for
test and interconnect.
The only way I could work out how to do this
easily in PCB was to make a new component
that was just 5 pins in a row and add them
in the schematic to the
On Sun, Sep 16, 2007 at 08:28:41AM +1000, andrewm wrote:
That is probably the nice way to do it and
makes things more followable. In protel
I just used to pop down vias and pads where
ever I felt like it and it would let me
connect them.
You can do that in PCB. There are two things to keep
After much wailing and gnashing of teeth at the grid alignment bug
here is my first PCB produced with gEDA/PCB
http://www.thehacktory.com/IR-simple-v1p52-top.png
http://www.thehacktory.com/IR-simple-v1p52-bot.png
It took several days because of learning curve and the grid bug
and there are
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