On Tue, Mar 3, 2009 at 6:03 PM, Stephen Williams [1]st...@icarus.com
wrote:
Larry Doolittle wrote:
Patrick -
On Tue, Mar 03, 2009 at 12:37:17PM -0500, Patrick Doyle wrote:
Should I have been able to find that somewhere else? (I am
asking in a tone of voice of I
Hello gEDA-ites... it's been a while since I've hung out on this list,
but I'm glad to see you're all still alive and kicking :-)
I have an Icarus Verilog question (which may, perhaps be a more
general Verilog question). I would like to write a test bench that
exits with a
Patrick -
On Tue, Mar 03, 2009 at 11:39:28AM -0500, Patrick Doyle wrote:
I have an Icarus Verilog question (which may, perhaps be a more
general Verilog question). I would like to write a test bench that
exits with a non-zero status when it detects an error. That way I can
Patrick -
On Tue, Mar 03, 2009 at 12:37:17PM -0500, Patrick Doyle wrote:
developers eventually added their own Verilog extension, the
VPI function $finish_and_return(exit_status).
Oh... I like that!
That's just what I was hoping my buddy Google would have found for
me.
Larry Doolittle wrote:
Patrick -
On Tue, Mar 03, 2009 at 12:37:17PM -0500, Patrick Doyle wrote:
Should I have been able to find that somewhere else? (I am
asking in a tone of voice of I would like to know where to look for
answers such as these so I don't have to pester the mailing
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