Re: gEDA-user: Icarus Verilog with Xilinx simprims...

When they said warnings and your on your own that means when you make something just barely function and have no safety margin logically coming form the spec sheet of the parts you used, you do not know when it will or won't work, at which temperature, or on which individual part from the

Re: gEDA-user: Icarus Verilog with Xilinx simprims...

Günter Dannoritzer wrote: Andy Peters wrote: Does iverilog support SDF backannotation? The SDF has the delay information. Here are some information about that and a link to a previous discussion: http://iverilog.wikia.com/wiki/Graffiti#SDF_support I added a section to your entry covering

Re: gEDA-user: Icarus Verilog with Xilinx simprims...

Evan Lavelle wrote: Günter Dannoritzer wrote: [...] Here are some information about that and a link to a previous discussion: http://iverilog.wikia.com/wiki/Graffiti#SDF_support I added a section to your entry covering the reasons for doing timing simulations (same URL). Haven't quite

Re: gEDA-user: Icarus Verilog with Xilinx simprims...

If you're doing an asynchronous design, then you're on your own! Current CPLD and FPGA methodologies don't lend themselves well to async design. Certainly the fitted design will have glitches, as delays through various paths will be different. The point of synchronous design is

Re: gEDA-user: Icarus Verilog with Xilinx simprims...

CSB wrote: If your design is purely combinatorial, then of course you will have glitches, and remember that a post-fit timing simulation will show you these glitches for the particular routing the tools just used, which may change for each place-and-route run as you tweak the design.

Re: gEDA-user: Icarus Verilog with Xilinx simprims...

Andy Peters wrote: Does iverilog support SDF backannotation? The SDF has the delay information. Here are some information about that and a link to a previous discussion: http://iverilog.wikia.com/wiki/Graffiti#SDF_support Cheers, Guenter ___

Re: gEDA-user: Icarus Verilog with Xilinx simprims...

On Mar 17, 2007, at 7:56 PM, CSB wrote: Wow, thanks for the quick responses ! Does iverilog support SDF backannotation? The SDF has the delay information. Ah ! Now you mention it, I remember removing a $sdf_annotate line from the generated verilog file. It was causing an error with vvp, so

gEDA-user: Icarus Verilog with Xilinx simprims...

Hi all, I am trying to use Iverilog along with xilinx's SIMPRIMS. Well, I managed, but I am getting strange results with simulations. I'll try to explain how I'm doing this (I'm new to CPLDs, Verilog and Icarus...) First, I generate the post-fit verilog module from Xilinx ISE project navigator.

Re: gEDA-user: Icarus Verilog with Xilinx simprims...

On Mar 17, 2007, at 3:15 PM, CSB wrote: Hi all, I am trying to use Iverilog along with xilinx's SIMPRIMS. Well, I managed, but I am getting strange results with simulations. I'll try to explain how I'm doing this (I'm new to CPLDs, Verilog and Icarus...) First, I generate the post-fit

Re: gEDA-user: Icarus Verilog with Xilinx simprims...

Andy Peters wrote: the static timing analyzer (using your timing constraints) tells you if you've met timing. If both are good, there's no need to run a post-fit simulation. Dr. Deming told us that the Asian focus on direction of most closely approaching perfection is a better goal than

Re: gEDA-user: Icarus Verilog with Xilinx simprims...

Wow, thanks for the quick responses ! Does iverilog support SDF backannotation? The SDF has the delay information. Ah ! Now you mention it, I remember removing a $sdf_annotate line from the generated verilog file. It was causing an error with vvp, so I just removed the offending line and