Hello Stephen
On 25/03/08, Stephen Williams wrote:
The -tfpga code generator for virtex is almost certainly trying
to implement your gates with LUT2 devices. It uses an INIT= attribute
attached to the LUT2 to specify the logic. That's pretty basic and
should work.
Looks like ngdbuild is
Hello Stephen
On 25/03/08, Stephen Williams wrote:
Since the Xilinx free tools for this chip don't include a synthesis tool
I've been trying to use Iverilog, with some success.
I'm surprised by that. I thought the webpack releases support
spartan chips of various sort via xst. However,
Darren Stevens wrote:
Hello All,
I've been trying to use a Digilent XLA development board fitted with a Xilinx
spartan XCS10 fitted.
Since the Xilinx free tools for this chip don't include a synthesis tool I've
been trying to use Iverilog, with some success.
I'm surprised by that. I
3 matches
Mail list logo
