Nested for loops don't seem to work in iverilog.
it would seem that only the inner loop is updated.
Consider the following:
module TestMultiplier;
reg signed [7:0 ] x, y;
wire signed [15:0] z;
initial
begin
$dumpvars;
for (x = -128; x 128; x = x
On 10 Mar 2007, at 9:58:51 PM, [EMAIL PROTECTED] wrote:
Nested for loops don't seem to work in iverilog.
it would seem that only the inner loop is updated.
Consider the following:
module TestMultiplier;
reg signed [7:0 ] x, y;
wire signed [15:0] z;
initial
begin
On Sat, Mar 10, 2007 at 10:11:32PM -0500, [EMAIL PROTECTED] wrote:
Nested for loops don't seem to work in iverilog.
it would seem that only the inner loop is updated.
reg signed [7:0 ] x, y;
for (x = -128; x 128; x = x + 1)
Stop right there. x128 is _always_ true, since
On 10 Mar 2007, at 10:18:41 PM, [EMAIL PROTECTED] wrote:
On Sat, Mar 10, 2007 at 10:11:32PM -0500, [EMAIL PROTECTED]
wrote:
Nested for loops don't seem to work in iverilog.
it would seem that only the inner loop is updated.
reg signed [7:0 ] x, y;
for (x = -128; x 128; x = x
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