On Wed, 06 Jan 2010 01:29:35 -0500, Stan Katz wrote:
> Done.
If the problem was a newbie misconception what a ratline is, then a
closer look at the tutorial might remove similar show-stoppers:
http://geda.seul.org/wiki/geda:gsch2pcb_tutorial
A list of all available tutorials can be foun
Done. Thank you gentlemen. I understand queries such as mine are
"clutter" in high quality list traffic, such as found here. Other such
lists have mercilessly sent me to /dev/null in the past. I appreciate
your kindness in responding.
On Wed, Jan 6, 2010 at 12:15 AM, John Griessen
Stan Katz wrote:
No matter
>how I draw the nets in gschem, the final rats nest runs produced in
>pcb is one trace, across all the pins on each side of the SOIC, as
>long as any of them are in the star end-run to the header pin. In
>other words, if I want to tie pins 1,3,5, of the
Rats don't short copper they travel across; they only electrically
connect their endpoints. It's up to you - the layout person - to put
copper (not rats) in the right places. PCB has some settings to help
with this, like auto-enforce DRC clearance which highlights pins in
the same net when you s
I use gEDA for small projects. One, and two sided boards only. It's
been fine up until now. I now have a transceiver chip with some pins,
a number of which I need to run to pin 1 on an IDE header. No matter
how I draw the nets in gschem, the final rats nest runs produced in
pcb is
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