Hello.
Am 29.04.2008 um 01:23 schrieb Stephen Williams:
Attila Kinali wrote:
On Sat, 26 Apr 2008 09:22:17 +0200
Hagen SANKOWSKI [EMAIL PROTECTED]
wrote:
Mostly bad VHDL design goes to FPGA, good Verilog design goes to
ASICs.
Uhm... I don't think i have to comment on something
On Fri, 25 Apr 2008 14:04:38 -0700
Stephen Williams [EMAIL PROTECTED] wrote:
As you know, this year's Icarus Verilog GSoC candidate is working
on a VHDL code generator back-end for Icarus Verilog. Hooray!
But suddenly the obvious question comes up, How are we going to
run these generated
Attila Kinali wrote:
On Fri, 25 Apr 2008 14:04:38 -0700
Stephen Williams [EMAIL PROTECTED] wrote:
As you know, this year's Icarus Verilog GSoC candidate is working
on a VHDL code generator back-end for Icarus Verilog. Hooray!
But suddenly the obvious question comes up, How are we going to
Attila Kinali wrote:
On Fri, 25 Apr 2008 14:04:38 -0700
Stephen Williams [EMAIL PROTECTED] wrote:
As you know, this year's Icarus Verilog GSoC candidate is working
on a VHDL code generator back-end for Icarus Verilog. Hooray!
But suddenly the obvious question comes up, How are we going to
On Sat, 26 Apr 2008 09:22:17 +0200
Hagen SANKOWSKI [EMAIL PROTECTED] wrote:
As a freelancer now 10 years in business I work nearly on a every day
basis with *both* languages, Verilog HDL and VHDL. In general, I see
two trends.
First, the serious and bigger the SoC design, the often
Stephen Williams wrote:
[...]
Has anybody here used ghdl? freehdl? Relative merits? Which is
most active? The most portable? Easiest to use?
It just seems like ghdl has the most activity associated with it,
but FreeHDL doesn't look completely dead either. So what to choose?
For openSUSE you
al davis wrote:
On Friday 25 April 2008, Stephen Williams wrote:
As you know, this year's Icarus Verilog GSoC candidate is
working on a VHDL code generator back-end for Icarus Verilog.
Hooray! But suddenly the obvious question comes up, How are
we going to run these generated files? I'm here
Attila Kinali wrote:
On Sat, 26 Apr 2008 09:22:17 +0200
Hagen SANKOWSKI [EMAIL PROTECTED] wrote:
Mostly bad VHDL design goes to FPGA, good Verilog design goes to ASICs.
Uhm... I don't think i have to comment on something uneducated
like this, do i?
Right, let's please not fall into this
On Monday 28 April 2008, Stephen Williams wrote:
Mostly bad VHDL design goes to FPGA, good Verilog design
goes to ASICs.
Uhm... I don't think i have to comment on something
uneducated like this, do i?
Right, let's please not fall into this pit. I was hoping the
mud would dry up and
Hello.
Am 25.04.2008 um 23:04 schrieb Stephen Williams:
As you know, this year's Icarus Verilog GSoC candidate is working
on a VHDL code generator back-end for Icarus Verilog. Hooray!
But suddenly the obvious question comes up, How are we going to
run these generated files? I'm here looking
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
As you know, this year's Icarus Verilog GSoC candidate is working
on a VHDL code generator back-end for Icarus Verilog. Hooray!
But suddenly the obvious question comes up, How are we going to
run these generated files? I'm here looking for
On Fri, 25 Apr 2008 14:04:38 -0700
Stephen Williams [EMAIL PROTECTED] wrote:
As you know, this year's Icarus Verilog GSoC candidate is working
on a VHDL code generator back-end for Icarus Verilog. Hooray!
But suddenly the obvious question comes up, How are we going to
run these generated
On Friday 25 April 2008, Stephen Williams wrote:
As you know, this year's Icarus Verilog GSoC candidate is
working on a VHDL code generator back-end for Icarus Verilog.
Hooray! But suddenly the obvious question comes up, How are
we going to run these generated files? I'm here looking for
13 matches
Mail list logo
