Done. Thanks a lot Paul.
--- On Mon, 11/22/10, Paul Tan wrote:
From: Paul Tan
Subject: Re: gEDA-user: control verilog module parameter order when
converting .sch and .sym with gnetlist?
To: geda-user@moria.seul.org
Date: Monday, November 22, 2010, 1:25 AM
Hi Chris,
On Sunday 21 November 2010, Chris wrote:
Btw: The bufif1 symbol from the verilog library get's compiled with
it's inputs in the wrong order. That is the gnetlist -g verilog
produced bufif1(IN,OUT,CNTRL) instead of bufif1(OUT,IN,CNTRL). How can
I change that? I changed the INPUT0 and IN
I change that? I changed the INPUT0 and INPUT1 statements in the
attributes of the pins, but that didn't change anything.
Cheers,
Chris
--- On Sun, 11/21/10, al davis wrote:
From: al davis
Subject: Re: gEDA-user: control verilog module parameter order when
conv
On Sunday 21 November 2010, Paul Tan wrote:
> Since most Verilog simulators (including Icarus Verilog)
> support "EXPLICIT connection" method for the lower level
> Module Instanciations, so it is not absolutely necessary
> (although desirable) to match the Module portname order
> with the Module in
Hi Chris,
Last time I checked, when netlisting a schematic, the
gEDA Verilog netlister does not order the top MODULE portnames
by user specified sequence order(such as using the refdes
attribute's numeric suffix value of I/O PADS to order the
portnames).
Since most Verilog simulators (including I
Hello mailing list,
I need some help here. I want to use gschem to create a hierarchical
design and simulate that using icarus verilog. "gnetlist -g verilog"
works fine, but I have some trouble figuring out how to create a
matching symbol for the schematic and using gnetlist to
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