Some things have indeed been done. At the very least, you can
explicitly list in $dumpvars the array words that you want to
dump. The list needs to be explicit to prevent the explosion
of traces when you have large memories in your design.
Denis Daly wrote:
Hi,
I'm trying to simulate a
Hi,
I'm trying to simulate a Verilog file with many multi-dimensional arrays.
e.g.
wire [31:0] bus[7:0];
It appears that these signals do not show up in the VCD file and thus can't be
viewed in GTKWave. This was confirmed back in 2001 by Steve Williams.
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