Hi
I have a similar problem. I am using pcb v20080202-2 on Ubuntu and have
found that certain pads do not appear in the solder mask when exported
as Gerber files. I wonder if anyone else has come across this problem
and any way of forcing all pads to be included.
Regards Richard
Thats funny, i'd rather HAVE my vias covered with solder mask.
On Fri, Apr 16, 2010 at 7:51 PM, Richard de Rivaz rich...@mdr.co.uk wrote:
Hi
I have a similar problem. I am using pcb v20080202-2 on Ubuntu and have
found that certain pads do not appear in the solder mask when exported
timecop wrote:
Thats funny, i'd rather HAVE my vias covered with solder mask.
Me too, but there's merit to both ways. I work with a guy who made all
the vias visible, but placed them so badly that stuff shorted to them
all the time - like a metal can from a crystal, *bad*. I had him just
I like to have my vias non tented. That is, little holes in the solder mask,
so that some bare metal is exposed. This comes handy for debugging. Is it
possible to configure pcb so that vias are exposed by default?
You can select the mask layer and press 'k' the appropriate number of
times
You could modify the sources to do that, but there's no runtime option to do so.
You could do this:
Enable soldermask layer
Select All
:ChangeClearSize(SelectedVias,=1,mil)
:MinMaskGap(SelectedVias,=3,mil)
Or write a quick plug-in to do it :-)
___
On Fri, 16 Apr 2010 07:16:53 -0400, gene glick wrote:
For me, if I need to solder to a via, it's easy to scrape the soldermask
off with an exacto.
Minimum sized vias are hard to solder (12 mil hole, 28 mil annular ring).
But you can push a patch wire through a non-tented via.
On Fri, 16 Apr 2010 15:55:06 +0200, Duncan Drennan wrote:
You can select the mask layer and press 'k' the appropriate number of
times until the mask clears the via.
I know. I wrote the corresponding pcb-tip in the wiki:
On Fri, 16 Apr 2010 12:34:29 -0400, DJ Delorie wrote:
You could modify the sources to do that, but there's no runtime option
to do so.
Where would the setting be located in the source?
You could do this:
Enable soldermask layer
Select All
:ChangeClearSize(SelectedVias,=1,mil)
Where would the setting be located in the source?
There are two calls to CreateNewVia() in src/action.c, both pass 0
for clearance. Change those.
Hmm. Quite a hassle when typed into the GUI. It might be a job for a non
interactive action script, though.
Edit gpcb-menu.res to map those
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