You guys are my heroes. :)
Yeah, but we look silly in capes.
Will we start seeing the minutes being posted? They're way behind.
Maybe they could go on the freedaug web site?
The next code sprint is next month (July) in Southern New Hampshire
;-).
Yes, I know all about that one ;-)
What's the crux of the heavy/light argument?
It boils down to do I offer the user a NAND gate, or a 74ALS00ND?
Why can't a symbol file have a light description, and an associated
heavy description in a separate file, and have it so when a user
adds the component, she chooses which 'heavy'
Thanks. Got past that problem and on to a new one. I have 10 mil
traces with 10 mil spacing between lines. The DRC fails unless I
have the minimum spacing set at 8.0 mils. Attached is a snippet of
the board showing the area in question.
I manually measured the distance between those two
DJ, When I do that it measures 10 mils. Both by the Ctrl-M and
setting the grid to 1 mil and counting.
Does your board look like this?
http://www.delorie.com/tmp/ggallant.gif
I count 8 mils between the light blue and the green.
I am using GTK-HID, I generated the gerber files with the export
option. I tried sending the .fab.gbr and they said not in Excellon
format.
Right, the fab drawing is a drawing - outlines, drill maps, notes,
etc.
So then I sent the .cnc file and they said your NC drill
file use tools which
I am using GTK-HID, I generated the gerber files with the export
option. I tried sending the .fab.gbr and they said not in Excellon
format. So then I sent the .cnc file and they said your NC drill
file use tools which are not defined. Any hints?
Rounding bug. I'm checking this patch in.
Not easily. You have to put something else over them to fill in the
gaps; it's something we've discussed before.
You could do that with the old PCB back in Xaw times. Am I right?
Yes, this isn't a new technique.
I am trying to connect a thru hole pin to a poly on the bottom
side. Top side has plenty of clearance. Best so far is thermals but
I would like more copper in contact with the poly.
Thermals are the right tool for the job, but if you need more, draw a
line over the pin to fill in the gaps.
When I did that it just created a clearance around the line in the
poly.
Undo that, deselect the new lines, arcs clear polygons setting. Or
use the 'j' key to change the Join of those new lines.
I guess you'd specify what sort of via (pad size, drill size, clear
size, soldermask size,thermal or solid connection)
Just use the current via settings.
and an x-spacing and y-spacing
Use the current grid.
and it would just drop them down every where it could where it
didn't cause a DRC
BTW: is it possible to change a via into a solid connection right
now?
Not easily. You have to put something else over them to fill in the
gaps; it's something we've discussed before.
If your previously laid-down tracks didn't have the clear flag set,
you can at least edit the .pcb file and add the clearpoly flag to
all the lines.
You can use the J key to selectively un-join lines, or Shift-J for
selected lines, but as it's a toggle, you can't just select *all* and
apply it,
Yes, I think. You'll need to find a program that converts gerbers to
milling files that the cam uses; gerber to autocad should be out there
somewhere. It isn't a gEDA-specific problem though.
I've talked about this before, and this is probably the weirdest
part of the new furnace controller, so I'm open for input.
Second try. Still no optos, but used the 2.5V idea to bias the first
stage MOSFETS, so that a floating output makes Vgs zero for both
MOSFETS, and an active signal
Finally got around to adding board flipping to the lesstif hid.
Tab = up/down flip (same key/action as Xaw pcb)
Shift-Tab = left/right flip
Ctrl-Tab = spin 180 degrees (by doing both flips)
This is tied in with the SwapSides setting (so you always see the
right silk) and the smart layer
I have some sot223 components that I need to make the tab pad a large
exposed copper area to behave as a heatsink(require like 1 square inch of
exposed copper). Is there a way to do this PCB? Do you have to make this
part of the footprint creation or could you add a copper rectangle to
I tried that but as I understand it to make the pad one of the pins
it has to be a line for a SMT part. I couldn't make the line any
wider than 6.3mm, PCB wouldn't let me make it any wider. Is there a
setting I have to change to make the top end of the line width
larger?
Try using the
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Is it possible to group all of the Vcc connections on a device to
one pin in the schematic? I remember seeing a reference to
something like this recently but I can't find it.
Maybe you saw one of my symbols, where I have multiple pins but only
one label for them?
I think that was it. I have an opamp with a bunch of power pins and I
didn't want to clutter the symbol. Yours looks like a good approach.
Also, if you have multiple gates/amps in a package, you can create one
slotted symbol for the gate/amp, and a separate box symbol for all the
power
Sweet!
I also tried to change the join of the polygon by pressing 's' over
it but it said 'Sorry, this object is locked'. But the polygon was
not locked. There was a bigger polygon over it which I locked
intentionally. I suggest all tools except lock tool to be
insensitive to locked objects.
I
I made the gerber hid use names compatible with pre-hid. Still need
to fix the plated vs unplated drills, and names of clear/draw internal
layers.
I made a simple file test.pcb with 5 vias and then exportet into
gerber. The result: test.copper0.gbr test.copper1.gbr test.fab.gbr,
but not drill file. Why is this happening? How do I get the
drillfile?
Bug. Fixed.
How can I export the back and front paste gerbers from PCB? It was
working with the old gtkPCB, but now it's gone with the HID. I'm
using GTK HID.
FYI I did fix this, don't recall if I mentioned it.
IMHO one problem with this patch is that if you *don't* have the big
poly locked, or even with just the small polygon, it's easy to
accidentally join the polygon to all its vias when you're trying to
change the join of a line passing through the polygon.
Perhaps a ChangeJoin(SelectedPolygons) ?
For large symbols with more than 64 pins a spread sheet program may
be faster, especially if you can copy some of the labels out of a
datasheet.
FWIW my sym2csv and csv2sym programs use a spread sheet too.
There is no advantage to though-hole stuff that I am aware of.
Aside from mechanical strength of items like connectors. For the
terminal posts on my furnace controller, for example, I oversize the
pad on the solder side to provide more pull-out resistance.
Yes, I know SMT connectors are
I am interested on SMT board as well. For making only 1 or 2 prototype
board, my concern is that, for example, I need to buy a roll resistors which
at least are thousands of them. In addition, can I have some advises on what
tools are necessary for doing SMT board.
Digikey sells cut tape
In the djboxsym enhancement request department, I'd love if it would
allow rotated text on the top and bottom. I've got some fancy A/D's
(AD7763) with 64 pins total that have 11 power pins (6 different
kinds!) and a slew of ground pins (2 kinds). I like to put power and
ground on the top
You have changed the gerber names 8-|
We might do it again, so don't react too quickly. For example,
the drill files are still called *.gbr instead of *.cnc.
Then do the same for the postscript filenames which I guess will be also
changed,
There is only one postscript file now, suitable
Wouldn't it be possible that PCB would be called commandline with
--export-gbr or --export-ps and it would just do an export from given
Not only possible, but it already does. Try pcb -h for help.
Is there a way how to get the singlepage postscripts from this? I need
single page postscripts for the toolchain.
Not at the moment, but you're not the only person to request this, so
I'll probably add such a feature at some point.
Is sampling in the pictures performed correctly?
You know,
Index: draw.c
===
RCS file: /cvsroot/pcb/pcb/src/draw.c,v
retrieving revision 1.51
diff -p -U2 -r1.51 draw.c
--- draw.c 19 Apr 2006 22:36:46 - 1.51
+++ draw.c 14 May 2006 02:06:25 -
@@ -423,5 +423,5 @@ static
Have you looked at the parts from Allegro?
Not until just now, but I don't see anything that would fit. Which
ones were you thinking of?
The gate drive BJT's, being single ended, can't pull the gates to
off actively.
Oops, forgot the pull-down resistors. Imagine a pair of pull-down
resistors from the MOSFET gates to the other supply ;-)
The reason for the emitter followers is to properly bias the MOSFET
gates when the GPIO is
How can I export the back and front paste gerbers from PCB? It was
working with the old gtkPCB, but now it's gone with the HID. I'm
using GTK HID.
Oops. I'll have to add it back in.
Is using the two pins to create an I2C port an option?
Well, I need to signal fast enough (and with sufficiently reliable
timing) to drive the 1wire bus. Besides, it's not a lack of pins
that's the problem (I can switch to the 144 pin version and gain 44
GPIO pins), it's the flexibility and
Could you please send a snapshot after you add it, hence the CVS is
down. Thank you.
Unfortunately, I have a bunch of other changes in my working area that
you probably don't want yet, and I can't separate them without the CVS
servers being up, so by the time I get something for you, you won't
I'm planning on being there, but I have no specific project to work on
(at least, not one that could be done in a day ;) I'll probably do a
fix/usability blitz since I'll have so many guinea pigs, er, pcb
users available to guide me.
I've talked about this before, and this is probably the weirdest part
of the new furnace controller, so I'm open for input.
The furnace controller will have eight of these I/O drivers, two per
zone. Nominally one for input and one for output, but in my case it's
one for the dallas 1wire
SymbolLine[1500 2500 2000 3000 800]
To which font are you referring? Mine still uses the () syntax, not
the [] syntax, and putting your line in results in a mess.
I didn't know we have a choice. It is whatever the web download
defaults to.
Which web download?
saved,
Ok, that's where the [] format comes from. PCB converts it when it
saves boards. Mine, saved, looks like this:
Symbol['5' 1200]
(
SymbolLine[0 1000 2000 1000 800]
SymbolLine[0 1000 0 3000 800]
SymbolLine[0 3000 500 2500 800]
SymbolLine[500 2500 1500
If you simply cut the font information out of the .pcb file, PCB will
re-load the default font from disk and insert it into the .pcb file.
The no touch service is $153 for 3 boards up to 60 square inches
6/6/15. I have used them, and they did a good job. They are in the
US, and take about 4 days.
I misremembered myspreadsheet (I'm in Georgia at the moment).
PCBex - qty 5 $158 7/7/15
pcbfabexpress - qty 5 $165 7/7/15
I think you are mixing up pcbexpress with a different vendor (maybe
expresspcb?). pcbexpress doesn't mind panelization. Last month I
did a panel with 10 layouts.
You're right, I was thinking of protoexpress. pcbexpress in my
spreadsheet is qty 2 for $290.
or qty 16 for $332 ;-)
And how many furnace controllers do *you* want? ;-)
every decent cad product can generate copper pour with hatch stroke fill
every decent fab house can deal with standard gerber files
I suspect that the effort required to support non-composite pours is
the same effort required for copper island removal. I.e. lots.
I am using the cheapest possible boardhouse for 4 layer.
Who? I've started peeking at 4 layer prototype deals for the second
furnace controller, the best deal for me seems to be $160 for three
3.5x5.5 boards at 7/7/15.
I'm using pcb 20050609, and one of the boards at
http://www.tartarus.org/~chris/tmp/pcb/
I was hoping for the *.pcb but the gerbers are sufficient. It looks
like a standard ground plane. Why do you have a copper outline around
each layer, instead of a separate outline layer?
Well, IPNEG
Then the core is currently defining the flip direction. Shouldn't
the macros SWAP_SIGN then be replaced with HID functions so the gui
can be in control?
No, the core is defining the physical flip direction - the direction
that elements are flipped when they're moved to the other side of the
Ok, so it's currently a vertical flip then since the gui only draws
primitives and there's no way to know what object they came from.
Right. The core says draw a line from A to B (A and B being board
coordinates) and the HID's responsibility is to determine where A and
B are on the
My board house[1] has complained about my gerbers having negative
plots and composite layers.
Can you send us examples? Which PCB are you using (hid or pre-hid)?
1) (Main question) How can I tell if my gerbers are negative and/or
composite so I can check?
In the gerber file itself, look
My fab correctly interprets the LPC command. To them the trouble is
the layer command %LNCUTS%. After I manually removed all these lines
from the gerbers, the files were ok with them. Maybe Olimex is
different from Basista. But I suspect, it's the same issue in this
case.
I suspect we need
Move the big rectangle to a different layer, either temporarily or
elsewhere in the layer group. Then you can disable that layer.
I just noticed, that mechanicals in datasheets are sometimes in an
integer scale, eg. 4:1. It could be very handy to see an image of
the mechanicals in the background in PCB when drawing the
footprint. And if I could see there a page of my PDF without copying
the image to an external file...
USAGE: pcb-bin [standard Gtk options] [standard options] [layout]
pcb-bin: 20060321
You need a newer snapshot to get background support in the gtk hid.
Use pcb -h to see all the options your current pcb supports. You
want this one:
--bg-image stringBackground Image
I'd like to put a simple relay footprint in PCB. Unfortunately, I
can't find any... Nobody uses relays these days?
There are so many types of relays... You're the one with the relay,
you'll have to measure it and figure out where to put the holes for
the pins, and create a simple footprint
No you don't. The postscript output doesn't contain any occurence
of the word setcolorspace.
It doesn't have to. setgray and setrgbcolor also set the colorspace.
setcolorspace is only needed if you call setcolor, which we don't.
OK understand. However I still wonder if the Postscript actually
defines a device-independent shade of gray (this is quite easy to
define physically as a fraction of white photon flux).
I don't think so. They do define transfer functions and halftone
functions to allow you (or the printer)
I would like to display the postscript on my laptop. Black means 0
photons per some time and white means 100 photons. How many photons
is the gray supposed to have per the same time?
I don't know. It depends on, among other things, the gamma of your
monitor and the gamma settings for your X
I asked what the gray is supposed to be. You say that it depends on
the gamma setting of my X software. Supposing is an action of human
mind. Does it mean that the person who decided the postscript
generation can not only remotely read the setting of my X server,
but can also do it against
I suggest to use CIEbasedA space instead which is device
independent.
The use of CIE color spaces is incompatible with our desire to be
compatible with Level 1 postscript devices.
I just added a --psfade option to control how faded the assembly
drawing is. It takes a value from 0.0 (essentially omitted) to 1.0
(not faded at all).
But if you don't issue the setcolorspace command then the result is
implementation dependent.
Also there are convenience operators ... that select both a color
space and a color value in a single step. We use those, therefore we
*are* selecting a color space.
We do not use the setcolor
Some patches appeared shortly, what about not release a snapshot but
first release some release candidates (and return to a normal
versioning scheme)?
Snapshots are not supposed to be releases. I've mentioned to Dan that
we could make snapshots more often.
I agree, but the release of the first snapshot of the HID PCB could not be a
release? In the worst case, the 0.1 HID-PCB?
Well, yes, but that's a different topic ;-)
It has been suggested in the past to call the final HID release 4.0,
as the TCL/TK fork of pcb calls itself 3.0. The Xaw/GTK
Also of note, once you get pcb built, run pcb -h to get a list
of command line options. The double-dash options correspond
to X and Gtk resources. Example:
Command line:
pcb --grid-color '#ff'
.Xdefaults (lesstif):
pcb.grid-color: #ff
$HOME/.pcb/preferences (gtk):
grid-color
Good. However, something happened with actions, since the File-Load
does not work, nor File-Revert.
Here's a patch.
Index: global.h
===
RCS file: /cvsroot/pcb/pcb/src/global.h,v
retrieving revision 1.42
diff -p -U2 -r1.42
Sorry if I am a bonehead, but I have no idea how to apply a patch, can you
please explain?
diff -p -U2 -r1.42 global.h
--- global.h12 Apr 2006 22:51:02 - 1.42
Well, two ways. For simple patches like this one, you can just edit
global.h to reflect the change. It's just a
Is PCB compiled with Xaw unable to open a file written by GTK
version of PCB?
Older versions of PCB can't always load files created with newer
versions of PCB.
Can PCB always open file written by previous version of the program?
That's the goal, yes.
--draw it all in gschem and follow normal gschem -- PCB workflow
I'd do this anyway.
--trace pcb in PCB (can this be done?)
The Xaw version of pcb had this; you could scan the board and make it
your background image, then design over it. I should add this into
the lesstif hid.
I know of someone who makes a living from doing this with another
pcb design program. I would consider it an important component.
Ok, I added it to the lesstif HID in cvs. As soon as sourceforge gets
their anonymous cvs working, you can try it out.
Instructions and examples here:
When I do File-Export-gerber in pcb, it does not generate drill
(CNC) files. Is it normal? How can I make pcb to generate drill
files? PCB is from CVS.
Look for file.drill.gbr
1. The title should have been:
Well, the magazine is about *circuits* ;-)
2. The article is so well written that the real author should
stand forward.
I assume Stuart will take this as a compliment to his writing ability,
and not feel insulted that you don't think he's capable of
Ah...ok. And plated and unplated drills are merged?
Oh, crap. Yes, they're merged.
AFAIK many pcb manufacturers want a .cnc file along with the gerber data.
Are you sure it's no longer possible to generate these in current CVS?
It *is* a CNC file. It's just *called* .gbr.
DJ's promt reply makes me think a bit, but I don't know if he meant
crap becouse this fact is crap, or my point (which is sometimes
the case, so don't worry, I'm not hurt).
In this case, it was Oh crap, I got it wrong.
I need to fix it.
It *is* a CNC file. It's just *called* .gbr.
Why was it renamed?
No, the right question is, why hasn't it been renamed yet?
The file choosing code was part of the new HID interface, hence the
filenames are all different. It needs a little work (this is why
we're asking people to use HID
Could you send me your .pcb file?
I just checked in a fix for this. The fab drawing didn't compensate
for the fact that the drill report had total and unplated, yet wanted
plated and unplated. Just needed a subtract.
My pcb does not have such an menu named revert ! Windows shows 1.99a
version which is installed by CD install.
Revert is relatively new; only CVS has it at the moment.
Applied. Thanks!
Ahh, you too, eh? I downloaded the datasheets for that chip last
week. =)
I posted about that chip here, a few weeks ago. It's a sweet chip,
but it would be sweeter for me if it came in a 5V version that used a
1:1 pulse transformer.
OTOH the main reason for djboxsym is that I wanted to
J makes clearance but once saved, clearance disappeared.
Ok, we're back to did you get the patch that fixes the pcb forgets
to save arc clearances bug?
I wasn't looking forward to creating yet another box symbol, so
instead I spent far more time writing a tool to do it for me. Yeah,
I'm that kind of hacker. OTOH, the second symbol I used it for only
took a minute or so to create.
Similar in functionality to tragesym, with some differences:
*
Do the lines have the clear polygon flags set? This has come up
before; there's a number of recommendations in the mail archives.
Yes I did, only ARC portion touch with polygon.
Do you have the fix for pcb forgot to save the clears-polygon flag
for arcs ?
Currently I am manually loading up the element using File-load element
to paste buffer then manually replacing the 5 components and entering
the designator/value.
That's pretty much the only way at the moment.
If somebody were to write an open-source equivalent of Genesys 2000
(Valor), which is a CAM/DFM tool used by PCB fabs, they'd find
themselves the object of a lot of adoration from happy users!
Specs?
1) grow all soldermask relief by min_soldermask/2.
2) verify that all pads are in little islands of soldermask relief with
no other pads
Do we already check for too-small necks in polygon clearances? If so,
why not re-use that code?
Not at the moment, but it is on my list of highly desired features.
I've started a document describing what I'm hoping to implement.
I'll see if I can dig that out and post for comments.
Add anti-copper layers to the wish list. Use them to cut slots in
polygons. Also layers for extra mask
One of my biggest problems with this software so far has been my
difficulty in finding the complete set of information, from this
is how you spell P-C-B to references.
I've been working on this recently. At the moment, I'm adding
comments to the code for each action, which become both popup
- thermal spoke width is tied to the annular ring of the pad. I
think it is done to avoid funny bumps inside the drill area. But
the effect is the thermals on the top left via are not so hot when
compared to the lower left via
Thermal scale is currently board-level but we could override it
We already know antisilk won't work.
This is vendor dependent. APL's pcb shop uses GCCAM to process all
artwork, and anti-silk works just fine, for example.
Well, true, but I don't think it's something PCB should lead the user
to expect to always work. For example, we clipped silk over
I set via size in GTK PCB 20060321 in signal style to 25, OK, then
opened again and set to 24. Then I made a via and Object Report says
it has 23.99mil.
This seems to be a bug in the GTK units conversion (it works in
lesstif HID but fails in gtk HID). Try changing src/hid/gtk/gui.h
I tried implementing this once, but it slowed down PCB a lot. In my
case, it was square pads, and I was trying to squeeze another trace
out through the corner. I think I decided to just go with rounded
pads instead.
Note that this kind of slowdown would be even worse with layouts with
lots of
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