Stuart Brorson wrote:
At last Thursday's Free Dog meeting John Luciani brought his theremin,
which he had created in his home workshop. Not only did he design the
electronic part of the instrument using gEDA/PCB, but he also built the
unit into a large, wooden musical note which he hand
Mike Hansen wrote:
I run geda under virtualization on a windows box(yes I know pcb will
compile and work under cygwin but gschem is left behind, the mingw
compile is ages old, hence running on a linux box). Up until recently I
used qemu under windows. Performance is so so and not really a
Hans Nieuwenhuis wrote:
On Fri, 2 Jun 2006 09:02:55 -0500
Not that I know of, but maybe someone more experienced with PCB can give more info. As a
minimum I would suggest to put at least one via as close to every ground connection in
your schematic, preferably two (just in case one via ends
Donato Azevedo wrote:
Hi everyone,
I found on my father's garage, laying around a corner, a camm2 machine
http://www.cadigital.com/camm2.htm
and was wondering if I could use it to create PCBs. It was once used
to carve pictures into brass plates, so I figured: why not use it to
create printed
Wolfgang Buesser wrote:
Hi everybody,
probaly this is a stupid question, but I am having difficulties
generating a hierachical spice netlist: I have tried to follow the
instructions in the manual and ended up with the following netlist:
***
* Begin .SUBCKT model
Marc Price wrote:
Is there a quick and easy way to get 4v out using a
5v regulator l7805cv
I keep getting 5.04v tried adding a v resistor to the gnd
Marc :-P
do you mean you put a resistor in series with the gnd pin? That would
only let you go up from 5V, not down to 4.
You should get
Or maybe a silicon junction diode and a shottky diode. May get you a
little closer. Depends on the exact diodes and how much current you're
drawing. You could also stick in a npn transistor set up as a vbe
multiplier and pick the resistor values to give you the right thing.
-Dan
9000 VAX
Mike Hansen wrote:
I have a design that's very low production quantity(~50 pieces per year)
that has a couple of chips that only come in surface mount versions.
Does anyone have any opinions on what the lowest cost assembly option is
with the design, is it better to attempt to do the whole
You can buy small quantities of SMT resistors from a number of sources
like DigiKey or Mouser just to name a few. In terms of tools, a fine
tip soldering iron, a pair of tweezers, and decent light will get you
going. For rework, a hot air gun with a fine tip is pretty darn useful.
-Dan
hwb
Phil Taylor wrote:
You can get a solder paste syringe sample kit from a company called EFD.
It'll last you for a long time doing prototypes.
I've seen a nifty system (maybe the same thing) which you hook up to
compressed air and a foot pedal. One press gives you a little bit of
paste. I
Darrell Harmon wrote:
From the Sierra proto express design rules:
Minimum trace space: 6 mil
Minimum width of Annular Ring: 5 mils
When I set the DRC in PCB to these values and create vias with a 5 mil
annular ring, I get:
17: Rules are minspace 6.00, minoverlap 4.0 minwidth 5.99,
Darrell Harmon wrote:
On Sat, May 06, 2006 at 02:32:39AM -0400, Dan McMahill wrote:
To clear up any confusion, it should be noted that digital IF and software
defined radio techniques are used. I am samping at 62.5 MHz.
which ADC?
-Dan
Darrell Harmon wrote:
What is a good way to expose a ground plane for mounting a shield?
I have a board which needs to be very well shielded, and am planning
on making a machined aluminum plate with compartments for each
section of the circuit. The board will screw to this instead of
Marc Price wrote:
Seen as the Tesla coil mailing list is down i thought i might ask this
question here
i tested 2 x 2n3055 transistors and i read that you need to match the 2
but what
i dont know is, do i need to have them exact or just close.
transistor 1 gain Hfe = 123
transistor 2 gain
Darrell Harmon wrote:
I went with 1 via every mm. So far, I have 2110 vias, so I should be able
to stay under 2500 by the time I finish routing it.
I created a footprint by drawing the lines and vias on the board, and then
selecting all the parts of the shield box and creating an element
Stefan Dröge wrote:
I made a layout with gschem, and converted it with gsch2pcb.
But when I want to load the netlist file (AVR_ISP.net) pcb says Empty
netlist file!.
Here is the content of AVR_ISP.net:
unnamed_net13D3-1 J1-2
unnamed_net12J1-5 U1-5 U1-3 U1-7
unnamed_net11J1-9 R1-1
Dan McMahill wrote:
This is just a heads up for those who may be tracking CVS sources for
PCB. Sourceforge (SF) had some major hardware failures recently and CVS
was offline for several days. Developer CVS access has been restored
but SF has not turned on syncing of developer CVS to either
Stephen Williams wrote:
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Dan McMahill wrote:
VPI is sometimes called PLI-2. It is the way to go. The book
The Verilog PLI Handbook by Stuart Sutherland is _the_ reference,
you can also get some clues by looking in the vpi/ directory of
the Icarus
Anyone have a PLI routine which works with Icarus Verilog that can dump
out a hierarchy of a design? I'm looking to get an output like:
I1.I3.I7 - mymodule
I1.I4.I7 - mymodule
I1.I3 - mybigmodule
I1.I4 - mybigmodule
etc.
Thanks
-Dan
Anyone have a PLI routine which works with Icarus Verilog that can dump
out a hierarchy of a design? I'm looking to get an output like:
I1.I3.I7 - mymodule
I1.I4.I7 - mymodule
I1.I3 - mybigmodule
I1.I4 - mybigmodule
It's not PLI, but I wonder if you have checked out v2html? I'd be
Stephen Williams wrote:
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Dan McMahill wrote:
Anyone have a PLI routine which works with Icarus Verilog that can dump
out a hierarchy of a design? I'm looking to get an output like:
I1.I3.I7 - mymodule
I1.I4.I7 - mymodule
I1.I3 - mybigmodule
I1
VPI is sometimes called PLI-2. It is the way to go. The book
The Verilog PLI Handbook by Stuart Sutherland is _the_ reference,
you can also get some clues by looking in the vpi/ directory of
the Icarus Verilog source. All the system tasks and functions
are written using VPI.
ouch. Knowledge
I'm trying to use $realtime for some stuff with the 20060409 verilog
snapshot. I'm getting some funny results with $realtime and I'm not
sure if its me doing something stupid or it its a bug in verilog. FWIW,
verilog-XL gives the answer I think I should get.
`timescale 1ns/10ps
module
Stephen Williams wrote:
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Dan McMahill wrote:
Assertion failed: now.high == 0, file sys_time.c, line 126
Abort - core dumped
I can make that go away by commenting out a line where I do
x = $realtime; // x is a real
This appears to be a bug
Levente wrote:
Hello,
When I do break buffer elements into piece, pcb adds the hole flag to the
pins/vias.
Levente
I see the problem. I have a patch but I need to test it still. I
should have it checked in tonight.
-Dan
Levente wrote:
On Sun, 23 Apr 2006 15:34:59 -0400
Dan McMahill [EMAIL PROTECTED] wrote:
Levente wrote:
Hello,
When I do break buffer elements into piece, pcb adds the hole flag to
the pins/vias.
Levente
I see the problem. I have a patch but I need to test it still. I
should have
I've made a new snapshot of pcb. I made this one so quickly after the
previous partly because of the continued outage of the anonymous CVS
server which has prevented interested users from tracking CVS sources.
Also this snapshot fixes a couple of big bugs (load layout menu didn't
do
Markus Feldmann wrote:
Stuart Brorson wrote:
The geda program manager is deprecated. It hasn't been updated in
several years, and is showing signs of age. I suggest you just run
the tools from the command line.
Alternately, you can hack the source to run gnucap.
HTH and fG,
Stuart
Svenn Are Bjerkem wrote:
Even billion dollar tool creators like Cadence don't manage to make simulation
front-ends which really help the designers. A simulator front-end does not
need to be fancy, but it has to support a lot of simulator options. And since
there are at least more than two
Karel Kulhavy wrote:
On Wed, Apr 19, 2006 at 06:35:24PM -0400, DJ Delorie wrote:
I just added a --psfade option to control how faded the assembly
drawing is. It takes a value from 0.0 (essentially omitted) to 1.0
(not faded at all).
Still useless - I need the PostScript to define the gray
Hi,
I've put together a new snapshot of PCB. This is the first snapshot of
the HID version. We've been busy over the last several weeks and have
fixed a number of bugs and at this point we'd like some broader use and
testing of the HID version.
You may wish to take a look at the output of
This is just a heads up for those who may be tracking CVS sources for
PCB. Sourceforge (SF) had some major hardware failures recently and CVS
was offline for several days. Developer CVS access has been restored
but SF has not turned on syncing of developer CVS to either the
anonymous CVS
joeft wrote:
I've wondered about this since I started using PCB. I see it as one of
the biggest problems with the way PCB works. It should be truly
hierarchical and reference footprint info (with the proper scaling,
rotation, mirroring, attributes applied) rather than completely
embedding
Stuart Brorson wrote:
Is it a DRC failure? I have my boards full of such shit and I don't
care. I think the 1mil wide think cannot peel off and float because it's
held on both ends. Maybe it can get interrupted but I don't rely with
my groundplane connectivity on such thin places.
This should
Stuart Brorson wrote:
Maybe what's needed is a NA = not applicable pin type. This will
tell the DRC checker to not worry about the connection and report no
error.
IMHO, the utility of a schematic DRC check is in finding single pin
nets. THese are often the result of a real mistake, i.e.
Stuart Brorson wrote:
Min trace width/space
Min annular ring (i.e. min pad size over drill size)
Min soldermask clearance from pads
Min soldermask bridge width
Checking for metal slivers
I know that PCB does some checks (min trace width/space), but am not
so sure about min annular ring, a
John Doty wrote:
In my IC design work it would be useful to detect floating nets. DRC
tries, but since it doesn't understand globals or subcircuit I/O
connections, it screams about numerous non-problems, hiding the real
trouble. But a SPICE OP analysis is usually pretty effective here.
Stuart Brorson wrote:
PCB does min annular ring checks as of several weeks ago.
Great! THis is an important check! Thank you!
[ . . . .]
By soldermask bridge width do you mean minimum width in between
soldermask relief areas?
Yes. In particular, I am interested to check that the
DJ Delorie wrote:
1) grow all soldermask relief by min_soldermask/2.
2) verify that all pads are in little islands of soldermask relief with
no other pads
Do we already check for too-small necks in polygon clearances? If so,
why not re-use that code?
we don't as far as I can tell. I
ST de Feber wrote:
Hello,
I am used, Protel/Eagle, to work with keep out-line/layers.
Is it possible to have a similar thing in PCB ?
Not at the moment, but it is on my list of highly desired features.
I've started a document describing what I'm hoping to implement. I'll
see if I can dig
kmk wrote:
ST de Feber wrote:
Can PCB remove dead copper ?
No.
This is a feature still missing in pcb.
If anyone wants to contribute this, I'm sure it would be welcomed. I'd
recommend having an option that sets some area threshold so the user can
specify remove islands less than X
joeft wrote:
Dan McMahill wrote:
kmk wrote:
ST de Feber wrote:
Can PCB remove dead copper ?
No.
This is a feature still missing in pcb.
If anyone wants to contribute this, I'm sure it would be welcomed.
I'd recommend having an option that sets some area threshold so the
user
DJ Delorie wrote:
PS: What's APL?
probably the Applied Physics Laboratory at Johns Hopkins
(http://jhuapl.edu/)
-Dan
Hans Nieuwenhuis wrote:
Hi,
I tried to compile the CVS version of PCB today, but compilation failed with
the following error:
gcc -DNDEBUG -g -O2 -I/usr/X11R6/include -DXTHREADS -D_REENTRANT -
DXUSE_MTSAFE_API -I/usr/include/gtk-2.0 -I/usr/lib/gtk-2.0/include -I/usr
/X11R6/include
Subject pretty much says it all. Does anyone use the output of that?
Does anyone know what to do with it?
-Dan
Karel Kulhavy wrote:
I double-click GND in the netlist and pres 'e' and 'w'. The ratnest on
GND is still there.
The manual says:
A disabled net is treated as if it were not in the net list. This is
useful, for example, if you plan to use a ground plane and don't want
the ground net showing up
would swear I saw your problem with
your board 20 minutes ago but now I don't. I'll try to get back to this
later. Have to run out right now.
-Dan
# release: pcb-bin 1.99q
# date:Sat Mar 25 10:00:49 2006
# user:dan (Dan McMahill,At Home ,258-8142,)
# host:bondage
PCB[ 20
Dan McMahill wrote:
Levente wrote:
On Sat, 25 Mar 2006 15:27:49 +0100
Levente [EMAIL PROTECTED] wrote:
I think HID_GTK does not show the elemetarcs correctly. With lesstif,
everything is working fine. I have problems with the SO8 packages,
and only
the horisontaly aligned ones. Note
DJ Delorie wrote:
Do you have a way to tell how the interference is getting in? Is it
the supplies or the signal lines?
The only thing I've *seen* is a pulse on the latch line from the
computer to the latch. Remember, I'm just using the parallel port,
and there's a 10 foot ribbon cable
Steve Meier wrote:
Has anyone got a list of standard drill sizes
one of the appendices of the pcb manual does.
-Dan
Didn't configure complain that gd was missing along with explicit
instructions on how to get it?
did you see something like this?
[snip]
checking for gdlib-config... /usr/pkg/bin/gdlib-config
checking for libgd cflags... -I/usr/pkg/include
checking for libgd libs... -L/usr/pkg/lib
A number of people have had various problems building PCB documentation
from CVS sources. I have just checked in several changes to help
address these problems.
Building from a distfile
Nothing special should be needed. You should end up
DJ Delorie wrote:
Keep in mind, this board is mounted inside a five-sided metal box,
which is mounted on the metal air duct coming out of our furnace.
This is the same furnace that includes a couple of induction motors,
an electrostatic air cleaner, fire, water, refrigerant, and 18 gauge
wires
Philipp Klaus Krause wrote:
gerbv crashes on startup with [EMAIL PROTECTED]
It works with LANG=C
I just added this to the Debian bugreport at
http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=302530
thats probably a good bug report to put on the gerbv bug tracker instead
of the debian one.
kmk wrote:
John Luciani wrote:
:ChangeSize(SelectedLines,-4,mils)
Is there a command to set the line size to a value, rather than
increment or decrement it?
from the manual:
If value begins with a + or - then the value will be added (or
subtracted) from the current size, otherwise
Philipp Klaus Krause wrote:
In my drill helpers file generated by pcb it says:
There are 6 different drill sizes used in this layout [...],
even though I only used 3 different drill sizes. The first 4 drill sizes
in the list below the cited line are all 0.024 inch, plated.
Philipp
could you
Philipp Klaus Krause wrote:
Philipp Klaus Krause wrote:
I have created some custom pcb footprints, but their soldermask
clearance is way too big: The pads onb my PLCC32 and smd resonator are
free from soldermask, but everything in between them, too.
I already tried
Randall Nortman wrote:
On Wed, Mar 22, 2006 at 04:47:13PM -0500, Phil Taylor wrote:
Randall,
I was talking about file type footprints. Are you using python to make m4
scripts or to make file-type footprints?
Sorry, I wasn't clear, I meant that I first tried m4, and then gave up
on it and
DJ Delorie wrote:
The question I have is where the rounding happened. My assumption
is it was in the dialog where you adjust the active sizes. I can
take a look there and see if I can reproduce this.
Well, there's two parts: First, how did we end up with two
not-quite-perfect sizes, and
DJ Delorie wrote:
XENVIRONMENT=./Xdefaults.tgif true -print -color -eps ./pad.obj
We didn't change anything in docs, newlib, etc. Just src.
In your case, you need to install the tgif package. It's set to
true because it didn't find it.
One of the things HID buys us is the ability to
I have made a new snapshot for pcb. It is anticipated that this is the
last snapshot using only the GTK gui and that further releases will be
based on the HID version of pcb.
The new release may be found from the pcb sourceforge web page at
http://pcb.sf.net
The release notes are attached
Change all the - to _. Also you might look for the setting which
says search newlib before m4lib. This sounds like that name with dashes
is getting fed into m4lib which does not like - at all.
-Dan
hiroshi wrote:
When I changed the footprint name from
SOD123-370L1-160W__On-Semiconductor,
Karel Kulhavy wrote:
Hello
Someone wrote that CVS PCB now displays the footprint attribute in the
footprint library. I would like to try it out. Is the CVS PCB stable
enough? Does it often crash while losing the work? Does it sometimes
corrupt the .pcb file? Is it's file format compatible with
Dan McMahill wrote:
Karel Kulhavy wrote:
Hello
Someone wrote that CVS PCB now displays the footprint attribute in the
footprint library. I would like to try it out. Is the CVS PCB stable
enough? Does it often crash while losing the work? Does it sometimes
corrupt the .pcb file? Is it's file
I've added the footprints from PCB to gedasymbols.org. They are at
http://www.gedasymbols.org/footprints/.
In the M4 Libraries section, the link name is also the name you should
use for the gschem footprint= attribute.
Hope this is useful.
-Dan
Ales Hvezda wrote:
[snip]
Shoud I use gschem2xpcb instead of gsch2pcb ?
No you should use gsch2pcb. Where did you find a reference or
mention of gschem2pcb? Please let me know so I can remove it. Thanks.
Actually he said gschem2xpcb which is YAFAT (yet another forward
John Sheahan wrote:
Xtian Xultz wrote:
Can you say me the IC part number, I will take a look at the
datasheet, maybe I have a good idea (but I dont think I will)...
look at for example a Xilinx virtex 2 pro, perhaps the 2VP7.
john
I wonder if we should come up with an attribute for
hiroshi wrote:
Is ther anybody wha has footprint of 1808 ?
I can not find the sizes.
Thanks
Hiroshi
From IPC-7351, a nominal condition for a CAPC4520X168N footprint (4.5
mm x 2.03mm x 1.68 mm) you'd have
pad X = 2.30 mm
pad Y = 1.20 mm
pad spacing = 4.30 mm
If you orient the part with
The library window in the cvs version of pcb now lists in [] the correct
value for the footprint= attribute for all of the pcblib footprints (all
2,000 or so). For the newlib footprints, the displayed name is the
footprint= name.
Been meaning to get this done for a while but finally found a
Vanessa Dannenberg wrote:
On Sunday 12 March 2006 15:48, [EMAIL PROTECTED] wrote:
There's a lot of latitude as to what constitutes a schematic.
As long as you have a working process to generate a netlist from
source material, you're OK. Two nominally independent schematics,
and a bit of
DJ Delorie wrote:
Odd, I suppose it could be a version mismatch, I'm using a copy of
PCB fetched from CVS a week or two ago. If the first line is line 1
(rather than 0) then line 11 just specifies the DRC rules for this
board.
Dan's been adding DRC settings, so you'll need a newer PCB to
Vanessa Dannenberg wrote:
On Sunday 12 March 2006 20:02, Dan McMahill wrote:
Do you have docs for the eagle netlist format? Or for
that matter, does it look fairly simple? If so, it shouldn't be hard to
make one.
Netlist
Exported from Quickscan-0.1.2.sch at 3/12/2006 20:14:27
EAGLE
DJ Delorie wrote:
Ok, I spent some time on the pcb docs. I sent it off to Dan for
review, but a preview of the new content is here:
http://www.delorie.com/pcb/pcbfile.pdf
These docs are taken from contents in the pcb source file, so
hopefully they'll stay in sync with reality in the future.
Randall Nortman wrote:
Overall, reflow soldering is much faster. You spend a long time
placing each component, but then the soldering itself happens for the
whole board at once, in just a few minutes. The process is remarkably
forgiving of placement errors with these fine-pitch chips -- the
Vanessa Dannenberg wrote:
By the way, there's an infinite loop in the build, related to the ./doc
directory.
probably my fault, can you elaborate on which is causing the problem?
-Dan
DJ Delorie wrote:
If the board has an 'outline' or 'route' layer, the autorouter should avoid
placing 'traces' on this layer.
Yeah, the autorouter doesn't know about the outline.
Nor does it have a generic keep out layer.
after the HID conversion, keepouts are high on my hit list.
Vanessa Dannenberg wrote:
I figured I'd google a bit for this problem, as I could *swear* someone here
in the list mentioned an error similar to this.. It seems the autorouter
doesn't like to route to surface-mounted parts...or at least, the ones I
created to implement a basic edge connector.
Karel Kulhavy wrote:
I am slowly starting to suspect that PCB is also one of these projects
because I sent a patch and didn't even get a reply whether it will be
used ot not, set apart being actually applied.
what is the patch submission number?
-Dan
Karel Kulhavy wrote:
On Mon, Feb 27, 2006 at 12:11:22AM +, Marc Price wrote:
Ive tried multiple times now using Grep to find the footprint for a
resistor i add it and it doesnt work! every time i try it either uses
the wrong footprint or says error, surely a footprint selector of some
DJ Delorie wrote:
No - the symbol for DE9 cannot have any different labeling except
for 1-9 because it's a universal part. It can be used for anything,
not only for serial port.
Unless you like to have the symbol reflect the physical layout
You seem to be ignoring the fact that the male and
Stuart Brorson wrote:
Is there a free software tool to perform a layout extraction to get the
parasitics associated with the layout?
For IC design/layout, I believe that the open-source tool Magic will
extract the parasitics to a SPICE netlist.
For PCB layout, there is no tool, at least as
Dan McMahill wrote:
Stuart Brorson wrote:
Is there a free software tool to perform a layout extraction to get the
parasitics associated with the layout?
For IC design/layout, I believe that the open-source tool Magic will
extract the parasitics to a SPICE netlist.
For PCB layout
Karel Kulhavy wrote:
I suggest that DRC pre-loadable defaults according to IPC-A600D would be
added. Example: http://www.pragoboard.cz/czech/index_cz.htm
Does anyone have a copy of IPC-A600D?
you can preview the TOC here:
http://www.ipc.org/TOC/IPC-A-600G.pdf
It's not immediately obvious
John Luciani wrote:
On 3/3/06, Vanessa Dannenberg [EMAIL PROTECTED] wrote:
Perhaps it would be a good idea to show the user normal everyday words in
stead of 'refdes' and 'slot' and whatever else. It makes a lot more sense at
first, and seems less daunting. When I'm confronted with weird
kmk wrote:
Hi,
as you can tell from my mails, I am about to dive into pcb.
First thing I did was, to design a footprint PENTAWATV for the L165
Power Opamp. I started with pcb and thought, I'd finish with an editor.
The pin definition in my file looks like this:
/
| Pin[0 0 6600 2000
kmk wrote:
Hi,
what is the best method to do an update of footprints in pcb? Suppose I
improved my 0805 footprint with a fancy silkscreen. How do I transfer
this information to already existing layouts? I can't seem to find the
right button for this task.
Maybe I missed some important doc...
kmk wrote:
Dan McMahill wrote:
Clearly, the docs I am looking at do not reflect the file format used by
my installed version of pcb. Is there any other place to look for the
syntax?
The manual has been updated after your snapshot to address this.
The snapshot I use is http
kmk wrote:
Dan McMahill wrote:
unfortunately, no. This is, in my mind, a major limitation.
I've used
awk or emacs in the past. This is one of the things I'd really like to
see fixed. If anyone is up for some coding, they should contact me as I
think I understand the problem
Dan McMahill wrote:
Maybe my lib is outdated. I use the pcb package from debian testing
pcb-20050609-1...
now I'm really confused. In your email from an hour ago you said you
used the cvs version...
sorry, seems the rest of my response got erased before I sent it.
The IPC footprints
can't find the thread I meant to reply on
Someone had commented that lesstif is old and out of date and I think
questioned why use it at all.
One of the big values of all the work DJ has put into creating the HID
version of PCB with both lesstif and GTK gui's is that having 2 GUI's
Vanessa Dannenberg wrote:
What would cause PCB to not properly maintain it's rats nest and/or netlist?
In particular, over the course of adding rats to a board I'm working on,
moving parts, changing out parts for others, etc., PCB has made a mess of the
netlist it saves with the board. The
joeft wrote:
If I understand your description correctly, you need to raise the
impedance of the 2.5cm wire at 200 MHz to keep it from conducting
interference to the outside of the box. Is this wire used for power?
If so, get a ferrite core (toroid) and put it over the wire; pass the
wire
DJ Delorie wrote:
* Manually open the board from the Project Manager. PCB will report that
there is no font information included in the board, and that it's reverting
to the default font.
This is normal, although I suppose we could just not bother with that
message.
* You'll see a single
Vanessa Dannenberg wrote:
On Thursday 02 March 2006 18:28, DJ Delorie wrote:
Otherwise, yeah, an action script might be the best way to import
changes into pcb while it's running.
Rather than that, how about a function analagous to XMMS' commandline options?
That is, if XMMS is already
Ales Hvezda wrote:
* Call up the Library window, and select a simple part like a 7400. Move the
mouse over the gSchem window (and set your focus to that window if
necessary). Without clicking to place the part onto the schematic, change
the zoom level with z/Z. Now move the mouse a little
Ales Hvezda wrote:
[snip]
Older pcb's didn't support netlists *in* the pcb file itself. Since
we do now, perhaps gsch2pcb could just put the netlist in the newly
created file?
Sounds like a good idea. Anybody have some spare cycles to
tackle this?
In case someone beats me to
DJ Delorie wrote:
There are a couple of different ways to specify pads. The
documentation shows you one of them; your file uses a newer one.
The newest format is (from src/parse_y.y):
The manual is also explicit about this:
As Pcb has evolved, the file format has changed several times to
Anyone have experience using this for communicating bare board test info
to a board vendor? Or can vendors just extract this from RS-274-X and
NC-Drill files?
Is this something that it would be of value to have PCB export?
-Dan
Karel Kulhavy wrote:
On Sun, Feb 26, 2006 at 10:46:38AM -0500, Dan McMahill wrote:
Karel Kulhavy wrote:
Another thing to prevent mistake is to have a builtin list of common
processes. Like 0.35mm copper, 0.3mm gap, 0.2mm silkscreen. That's used
very often. If you enter one of those numbers
Marc Price wrote:
Ok Thanks John And Delorie all noted i just learned without the manual
how to grasp the part hold and move the part it moves the track with it
:-P so where is the PCB manual stored.
Marc 8-)
Try looking at the pcb home page.
Also try man pcb.
-Dan
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