Stephen Williams wrote:
That works for me. It simulates fine, and it synthesizes too. I think
there is something more to your problem then this. I'm using 0.8.
Actually, I hadnt tried that specific code. I often get errors,
something along the lines of:
Async if statement has no else statement
e
Charles Lepple wrote:
sorry for the confusion-- that doesn't synthesize in iverilog, either.
I apologize for the confusion as well. I didn't actually test that code
I posted before.
-d
On Thu, 06 Jan 2005 16:09:03 -0500, Thomas A.D. Riley
<[EMAIL PROTECTED]> wrote:
> The "always @(posedge clk or en):
> begin simulates in Icarus but won't synthesize in some commercial tools.
> So what to do depends on what you want.
sorry for the confusion-- that doesn't synthesize in iverilo
David Howland wrote:
Say I want to make a clocked, enabled register. This would simply be
the following in behavioral verilog:
always @(posedge clk) begin
if (en) begin
Q <= D;
end
end
That works for me. It simulates fine, and it synthesizes too. I think
there is something
On Thu, 2005-01-06 at 16:01, Nikholas Hubbard wrote:
> On Thu, 06 Jan 2005 14:45:07 -0500, David Howland
> <[EMAIL PROTECTED]> wrote:
>> Say I want to make a clocked, enabled register. This would simply be
>> the following in behavioral verilog:
>>
>> always @(posedge clk) begin
>
> what
Nikholas Hubbard wrote:
always @(posedge clk or negedge en) begin
Wouldnt this make it possible for the register to latch a value, even if
the clock is not high?
-d
MAIL PROTECTED]>
To:
Sent: Thursday, January 06, 2005 12:54 PM
Subject: Re: gEDA-user: Register enables in Icarus
On Thu, 06 Jan 2005 14:45:07 -0500, David Howland
<[EMAIL PROTECTED]> wrote:
Say I want to make a clocked, enabled register. This would simply be
the following in behavioral ve
On Thu, 06 Jan 2005 14:45:07 -0500, David Howland
<[EMAIL PROTECTED]> wrote:
> Say I want to make a clocked, enabled register. This would simply be
> the following in behavioral verilog:
>
> always @(posedge clk) begin
what if you try:
always @(posedge clk or en) begin
with Icarus
Say I want to make a clocked, enabled register. This would simply be
the following in behavioral verilog:
always @(posedge clk) begin
if (en) begin
Q <= D;
end
end
That verilog will work with most tools, but it seems to me that if I
want to use Icarus synthesis, I have to
