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It is a shortcoming of the fpga code generator. Your code is probably
synthesizing correctly, but the fpga target (at least for the part
family you are using) does not have the code generator support yet.
That is what the message is saying.
Mark All
Does anyone know if this is really an error or is it just
a shortcomming of the fpga type in the iverilog compiler?
I am doing designs which I eventually want to impliment on
altera.
Here is the snippit of code that caused this:
module tester (clk,ct
