Re: [gem5-dev] Review Request: Cache: Handle invalidation of temporary blocks correctly

2012-07-06 Thread Andreas Hansson
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1294/#review3056 --- Any tests to confirm: 1) that it works :), 2) that it does what it is

[gem5-dev] Cron m5test@zizzer /z/m5/regression/do-regression quick

2012-07-06 Thread Cron Daemon
* build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic FAILED! * build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp FAILED! * build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp FAILED! *

[gem5-dev] Review Request: Fix: Address a few benign memory leaks

2012-07-06 Thread Andreas Hansson
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1295/ --- Review request for Default. Description --- Changeset 9086:b2cb60523e6f

Re: [gem5-dev] Review Request: Bus: Make the default bus width 8 bytes instead of 64

2012-07-06 Thread Andreas Hansson
On July 4, 2012, 4:27 p.m., Steve Reinhardt wrote: Ship It! Steve Reinhardt wrote: Actually I'm now having second thoughts about this. The bottom line is that people really need to carefully specify bus bandwidths for a realistic system, and no one default is going to be

Re: [gem5-dev] Review Request: Cache: Handle invalidation of temporary blocks correctly

2012-07-06 Thread Nathanael Premillieu
On July 6, 2012, 12:12 a.m., Andreas Hansson wrote: Any tests to confirm: 1) that it works :), 2) that it does what it is intended to do? At least it has corrected the problem I had with some of my simulations. So from my point of view, the answer is yes to the two questions :) -

Re: [gem5-dev] Review Request: Bus: Make the default bus width 8 bytes instead of 64

2012-07-06 Thread Steve Reinhardt
On July 4, 2012, 4:27 p.m., Steve Reinhardt wrote: Ship It! Steve Reinhardt wrote: Actually I'm now having second thoughts about this. The bottom line is that people really need to carefully specify bus bandwidths for a realistic system, and no one default is going to be

[gem5-dev] Review Request: Port: Hide the queue implementation in SimpleTimingPort

2012-07-06 Thread Andreas Hansson
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1296/ --- Review request for Default. Description --- Changeset 9102:6e82c795f7c3

[gem5-dev] Review Request: Mem: Make members relating to range and size constant

2012-07-06 Thread Andreas Hansson
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1297/ --- Review request for Default. Description --- Changeset 9103:9c5e388abf87

[gem5-dev] Review Request: EventManager: Remove the queue member function and operator

2012-07-06 Thread Andreas Hansson
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1298/ --- Review request for Default. Description --- Changeset 9104:a3655fd63449

Re: [gem5-dev] Review Request: Cache: Handle invalidation of temporary blocks correctly

2012-07-06 Thread Steve Reinhardt
(I started to write this as a reviewboard comment, but it got kind of long...) I can see how this might work, but it seems a little obscure. In particular, it's not obvious that checking blk-isValid() is equivalent to checking for the temp block. The fact that it works is due to a recent hack

Re: [gem5-dev] Review Request: Port: Hide the queue implementation in SimpleTimingPort

2012-07-06 Thread Steve Reinhardt
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1296/#review3062 --- src/mem/tport.hh http://reviews.gem5.org/r/1296/#comment3261

Re: [gem5-dev] Review Request: Mem: Make members relating to range and size constant

2012-07-06 Thread Steve Reinhardt
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1297/#review3063 --- Ship it! Ship It! - Steve Reinhardt On July 6, 2012, 6:37 a.m.,

Re: [gem5-dev] Review Request: Bus: Make the default bus width 8 bytes instead of 64

2012-07-06 Thread Ali Saidi
Also, it's not completely clear to me that the l1 l2 bus would be that narrow/slow Otherwise it seems like a good. It's probably at least worth defaulting the l1to@2 bus freq to be the CPU freq. Ali Sent from my ARM powered mobile device On Jul 6, 2012, at 9:10 AM, Steve Reinhardt

Re: [gem5-dev] Review Request: EventManager: Rename queue accessor and remove cast operator

2012-07-06 Thread Andreas Hansson
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1298/ --- (Updated July 6, 2012, 7:56 a.m.) Review request for Default. Summary (updated)

Re: [gem5-dev] Review Request: Bus: Make the default bus width 8 bytes instead of 64

2012-07-06 Thread Andreas Hansson
Hi Ali, Are you suggesting to change the BaseCPU.py addTwoLevelCacheHierarchy and pass a width and clock on the line: self.toL2Bus = CoherentBus() If so, setting the bus clock to self.clock? What about the width? 128-bits? Andreas -Original Message- From: Ali Saidi

Re: [gem5-dev] Review Request: Port: Hide the queue implementation in SimpleTimingPort

2012-07-06 Thread Andreas Hansson
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1296/ --- (Updated July 6, 2012, 8:03 a.m.) Review request for Default. Description

Re: [gem5-dev] Review Request: EventManager: Rename queue accessor and remove cast operator

2012-07-06 Thread Steve Reinhardt
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1298/#review3064 --- Ship it! Ship It! - Steve Reinhardt On July 6, 2012, 7:56 a.m.,

Re: [gem5-dev] Review Request: Port: Hide the queue implementation in SimpleTimingPort

2012-07-06 Thread Steve Reinhardt
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1296/#review3065 --- Ship it! Ship It! - Steve Reinhardt On July 6, 2012, 8:03 a.m.,

Re: [gem5-dev] Review Request: Bus: Make the default bus width 8 bytes instead of 64

2012-07-06 Thread Andreas Hansson
A bit of an update...the additional complication is that quite often the CPU clock is set _after_ everything is connected up. Hence, the self.clock doesn't work as intended. Suggestions? Push the patch as is with the associated updates or change something additionally before bumping the stats?

Re: [gem5-dev] Review Request: x86: logSize and lruSeq are now optional ckpt params

2012-07-06 Thread Brad Beckmann
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1292/ --- (Updated July 6, 2012, 1:50 p.m.) Review request for Default. Description

Re: [gem5-dev] Review Request: x86: logSize and lruSeq are now optional ckpt params

2012-07-06 Thread Steve Reinhardt
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1292/#review3066 --- Ship it! Ship It! - Steve Reinhardt On July 6, 2012, 1:50 p.m., Brad

Re: [gem5-dev] Review Request: ruby: changes how Topologies are created

2012-07-06 Thread Beckmann, Brad
Yes, I believe Jason is going to follow up this patch with further improvements. Brad From: Steve Reinhardt [mailto:nore...@reviews.gem5.org] On Behalf Of Steve Reinhardt Sent: Wednesday, July 04, 2012 5:25 PM To: Steve Reinhardt; Default; Beckmann, Brad Subject: Re: Review Request: ruby:

Re: [gem5-dev] Review Request: ruby: memory controllers now inherit from an abstract MemoryControl class

2012-07-06 Thread Beckmann, Brad
Good question. Probably one that is easier answered once a detailed classic memory controller is checked in. That may be a good incremental task on the way to merging MessageBuffers and Ports. Brad From: Steve Reinhardt [mailto:nore...@reviews.gem5.org] On Behalf Of Steve Reinhardt Sent:

Re: [gem5-dev] Review Request: ruby: tag and data cache access support

2012-07-06 Thread Brad Beckmann
--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1290/ --- (Updated July 6, 2012, 3:44 p.m.) Review request for Default. Description