[gem5-dev] changeset in gem5: arm: make the PseudoLRU tags the default for ...

changeset f3e9fe1600d6 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=f3e9fe1600d6 description: arm: make the PseudoLRU tags the default for the O3_ARM_v7aL2 the Cortex-A15 has a random replacement policy for its L2 cache. see the Cortex-A15 Technical

[gem5-dev] changeset in gem5: mem: refactor LRU cache tags and add random r...

changeset c00b5ba43967 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=c00b5ba43967 description: mem: refactor LRU cache tags and add random replacement tags this patch implements a new tags class that uses a random replacement policy. these tags pref

Re: [gem5-dev] Review Request 2312: Mem: adding a multi-level page table class

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2312/ --- (Updated July 28, 2014, 10:29 p.m.) Review request for Default. Changes ---

[gem5-dev] Review Request 2319: Mem: adding architectural page table support for SE mode

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2319/ --- Review request for Default. Repository: gem5 Description --- Changeset 10265