Re: [gem5-dev] Extending x86 ISA to support full SSE and AVX

Hi Ahmed, Thanks for your willingness to attack this. We're glad to help out to the extent that we can. The documentation on the wiki is a bit of a mess at this point; there was an effort to reorganize it that got stalled partway through, so sometimes there are two copies of certain documentatio

Re: [gem5-dev] Review Request 2442: dev: Use shared_ptr for EthPacketData

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2442/#review5400 --- Are the bool cast operators being used anywhere? It looks like you put t

Re: [gem5-dev] Review Request 2448: config: Add Current as a parameter type

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2448/#review5399 --- Ship it! src/python/m5/params.py

Re: [gem5-dev] Ethernet device doesn't work with O3 cpu model in X86 ISA

>From what I see the MTRRs are not used by gem5. On a real system I would >imagine the hardware would check MTRRs and PATs to determine if an access is >uncacheable or not. It seems that memory accesses to the range of physical addresses [0xC000-0x] are not marked as uncacheable by

Re: [gem5-dev] Creating a ARM-x86 heterogeneous system

Hi Ajith, That sounds like a very ambitious goal (and a lot of work). I¹d suggest the following intermediate steps: 1. Make sure the bits and pieces that are truly not ISA dependent are built once (not once per ISA as we do it today), and then put in a library (libmem.a, libdev.a etc) that is us

[gem5-dev] Creating a ARM-x86 heterogeneous system

Hi, We plan to create a ARM-x86 heterogeneous system for full system simulation to boot a heterogeneous operating system on top of it. I have started looking at the gem5 code to try and understand the modifications needed. Please correct me if I am wrong. 1. Currently the architecture selected i

Re: [gem5-dev] Ethernet device doesn't work with O3 cpu model in X86 ISA

How did you do this? My current understanding is that we need to support MTRRs to mark the PCI address ranges as uncacheable. -- Nilay On Mon, 8 Sep 2014, Mohammad Alian via gem5-dev wrote: Hi, For some reasons gem5 doesn't recognize that PCI device address ranges are uncacheable. I set UNC

[gem5-dev] changeset in gem5: arm: Use MiscRegIndex rather than int when fl...

changeset d469fdcd937e in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=d469fdcd937e description: arm: Use MiscRegIndex rather than int when flattening Some additional type checking to avoid future issues. diffstat: src/arch/arm/miscregs.cc | 14 +++

[gem5-dev] changeset in gem5: misc: Fix issues identified by static analysis

changeset 148b96b7bc77 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=148b96b7bc77 description: misc: Fix issues identified by static analysis Another bunch of issues addressed. diffstat: src/base/loader/object_file.cc | 7 +-- src/base/statistics.hh

[gem5-dev] changeset in gem5: arm: More UBSan cleanups after additional ful...

changeset cc13df09fa55 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=cc13df09fa55 description: arm: More UBSan cleanups after additional full-system runs Some incorrect casting to IntRegIndex, and a few uninitialized members in the i8254xGBe device.

[gem5-dev] Cron /z/m5/regression/do-regression quick

* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing passed. * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing passed. * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic passed. * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple