changeset cae494887847 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=cae494887847
description:
arm, tests: Forgot the system.terminal files for the new regressions.
diffstat:
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/system.terminal
changeset bd7c2aa12122 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=bd7c2aa12122
description:
arm, tests: Add 64-bit ARM regression tests
diffstat:
tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/config.ini
| 2431 +++
tests/long/fs
changeset 7e54a9a9f6b2 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=7e54a9a9f6b2
description:
cpu: Add drain check functionality to IEW
IEW did not check the instQueue and memDepUnit to ensure
they were drained. This caused issues when drainSanityC
changeset ca4438b6e39a in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=ca4438b6e39a
description:
tests: Update regressions for the new kernels and various preceeding
fixes.
diffstat:
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini
changeset e57f5bffc553 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=e57f5bffc553
description:
cpu: Add writeback modeling for drain functionality
It is possible for the O3 CPU to consider itself drained and
later have a squashed instruction perform
changeset b423e1d0735e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=b423e1d0735e
description:
arm, tests: Update config files to more recent kernels and create
64-bit regressions.
This changes the default ARM system to a Versatile Express-like system
that
changeset 2b416ef3b400 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=2b416ef3b400
description:
automated merge
diffstat:
src/arch/alpha/linux/process.cc |4 +-
src/arch/arm/linux/process.cc|4 +-
src/arch/mips/linux/process.cc |4 +-
src/arch/po
changeset f33fab6214c4 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=f33fab6214c4
description:
arm: fix bare-metal memory setup.
The bare-metal configuration option still configured memory with the
old scheme
that no-longer works. This change unifie
changeset 38c7a9ea7729 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=38c7a9ea7729
description:
cpu: Add support to checker for CACHE_BLOCK_ZERO commands.
The checker didn't know how to properly validate these new commands.
diffstat:
src/cpu/checker/cpu.cc
changeset 94d58056729f in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=94d58056729f
description:
mem: don't inhibit WriteInv's or defer snoops on their MSHRs
WriteInvalidate semantics depend on the unconditional writeback
or they won't complete. Also,
changeset d5554f97c451 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=d5554f97c451
description:
arm, mem: Fix drain bug and provide drain prints for more components.
diffstat:
src/arch/arm/table_walker.cc | 5 ++---
src/mem/cache/mshr_queue.cc | 3 +++
src/mem/d
changeset aa23216161fa in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=aa23216161fa
description:
arm: Mark some miscregs (timer counter) registers at unverifiable.
The checker can't verify timer registers, so it should just grab the
version
from the e
changeset 58d5d471b598 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=58d5d471b598
description:
cpu: Fix barrier push to store buffer when full bug in Minor
This patch fixes a bug where a completing load or store which is also a
barrier can push a bar
changeset aa46a8ae3487 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=aa46a8ae3487
description:
arm: Fix multi-system AArch64 boot w/caches.
Automatically extract cpu release address from DTB file.
Check SCTLR_EL1 to verify all caches are enabled.
di
changeset f2f1dbfd505e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=f2f1dbfd505e
description:
mem: have WriteInvalidate obsolete MSHRs
Since WriteInvalidate directly writes into the cache, it can
create tricky timing interleavings with reads and wri
changeset e278fa3086b5 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=e278fa3086b5
description:
arm: Don't speculatively access most miscregisters.
Speculative exeuction can cause panics in detailed execution mode that
shouldn't happen.
diffstat:
s
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Ship it!
Ship It!
- Ali Saidi
On Oct. 29, 2014, 3:01 p.m., Andrew Luk
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(Updated Oct. 29, 2014, 3:01 p.m.)
Review request for Default.
Repository: gem5
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(Updated Oct. 29, 2014, 3:01 p.m.)
Review request for Default.
Repository: gem5
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Review request for Default.
Repository: gem5
Description
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Changeset 10510
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing passed.
* build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor
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