[gem5-dev] ARM with Ruby

Hello everyone, I am working on a project where we plan to experiment with different cache architectures in gem5 on ARM architecture. I am not really sure about the choice between Classic or Ruby memory model. But as I see on the status matrix page of gem5 (http://www.m5sim.org/Status_Matrix )

Re: [gem5-dev] Review Request 2457: sim: EventQueue wakeup on events scheduled outside the event loop

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2457/#review5447 --- I think this patch and corresponding wakeup event - and subsequent exter

Re: [gem5-dev] Review Request 2469: mem: dram ctrl: correct errors due to busBusyUntil variable

Andreas, we record the "owner" of the cache block in the trace. This methodology simplifies the configuration dependencies on the checkpoint and has worked well for Ruby for 15 years. There is actually an old paper from MIT that describes a more complete way of recording the owner of a cache b

Re: [gem5-dev] Review Request 2458: sim: SystemC hosting

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2458/#review5446 --- There is an issue with this patch for cases when a checkpoint is being r

Re: [gem5-dev] Review Request 2468: Solved bugs while switching cpu models with the --repeat-switch command

> On Oct. 27, 2014, 5:13 p.m., Ali Saidi wrote: > > src/cpu/o3/lsq_impl.hh, line 178 > > > > > > If you have a chance to test the dev repository that would be great. I was busy but I tested the dev repository, it seems like

Re: [gem5-dev] Review Request 2468: Solved bugs while switching cpu models with the --repeat-switch command

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2468/ --- (Updated Nov. 7, 2014, 9:35 p.m.) Review request for Default. Changes --- Th

Re: [gem5-dev] Review Request 2430: config: Add the ability to read a config file using C++ and Python

> On Nov. 6, 2014, 7:48 p.m., Cagdas Dirik wrote: > > This patch seems to be broken for X86 when restoring from checkpoints. A > > sample test crashes with segmentation fault. Here are the steps: > > 0. Sample test program does int array manipulation and creates a checkpoint > > before computat

Re: [gem5-dev] There seems a bug in ruby/mesi_three_level.py

You should post your changes as patch on the review board (reviews.gem5.org). From the code the below, I am unable to find the lines changed. -- Nilay On Fri, 7 Nov 2014, nifan via gem5-dev wrote: Hi: I believe there is a bug in MESI_Three_Level.py. when I tried to run build/MESI_Three

[gem5-dev] Cron /z/m5/regression/do-regression quick

* build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing passed. * build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing passed. * build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic passed. * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/si