Re: [gem5-dev] Review Request 2928: mem: add a base packet class

> On July 6, 2015, 10:13 p.m., Andreas Hansson wrote: > > I'm not too fond of how this is done, since it essentially creates a base > > class that only adds baggage to the classic memory system. Is it not > > possible to align the two rather? Also, besides the bloat, I am also > > worried abou

Re: [gem5-dev] Review Request 2908: ruby: Fix checkpointing and restore

> On July 3, 2015, 4:24 p.m., Jason Power wrote: > > Hi Tim, > > > > Sorry to come back to this patch, but I just applied it and tried to test > > it and ran into a problem. When restoring the original event queue in line > > 187 of System.cc, I get an error that the event is already on the ev

[gem5-dev] Review Request 2951: ruby: Fix memWriteback() not to record auto-delete events

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2951/ --- Review request for Default and Ruby Reviewers. Repository: gem5 Description -

Re: [gem5-dev] pd-gem5: simulating a parallel/distributed system on multiple physical hosts

Gents, I’ll let Gabor expound on the value of the non-synchronised checkpoints. When it comes to the parallelisation, I think it is pretty clear that: 1. The value of parallelising a single(cache coherent) gem5 instance is questionable, and the cost of making gem5 thread safe is high. That said,

Re: [gem5-dev] pd-gem5: simulating a parallel/distributed system on multiple physical hosts

Thanks for participating in this conversation Steve. Beside the usefulness of unsync checkpoints which is arguable, my understanding is that it has some issues in terms of correctness. In the example that Steve laid out, after restoring from checkpoint, one node is doing simulation to catch up to

Re: [gem5-dev] Review Request 2773: ruby: slicc: Dynamically find+declare all MachineTypes

> On June 18, 2015, 9:38 p.m., Sooraj Puthoor wrote: > > Hi Joel, > > I have some minor concerns and some major concerns about this patch..:). > > Let me start with the minor concerns first: > > > > 1) If this patch is applied on top of Nilay's > > http://reviews.gem5.org/r/2550/ patch, gem5 w

Re: [gem5-dev] pd-gem5: simulating a parallel/distributed system on multiple physical hosts

Thanks for keeping the conversation going. Sorry to not be participating more regularly. At a high level, I still have concerns about both unsynchronized checkpoints and interaction with multithreading. *Unsynchronized checkpoints:* I'm still not completely clear on the MPI_Barrier() example. Let'

Re: [gem5-dev] Review Request 2928: mem: add a base packet class

> On July 6, 2015, 10:13 p.m., Andreas Hansson wrote: > > I'm not too fond of how this is done, since it essentially creates a base > > class that only adds baggage to the classic memory system. Is it not > > possible to align the two rather? Also, besides the bloat, I am also > > worried abou

Re: [gem5-dev] Review Request 2928: mem: add a base packet class

> On July 6, 2015, 10:13 p.m., Andreas Hansson wrote: > > I'm not too fond of how this is done, since it essentially creates a base > > class that only adds baggage to the classic memory system. Is it not > > possible to align the two rather? Also, besides the bloat, I am also > > worried abou

Re: [gem5-dev] Review Request 2901: ruby: replace global cycle counter w/ cycle per ruby system

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2901/#review6736 --- Ship it! Ship It! - Joel Hestness On June 26, 2015, 8:16 p.m., Brando

Re: [gem5-dev] Review Request 2776: ruby: cleaner ruby tester support

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2776/#review6735 --- configs/ruby/MESI_Three_Level.py (lines 103 - 120)

Re: [gem5-dev] Review Request 2934: mem: a simple HMC controller

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2934/ --- (Updated July 8, 2015, 2:44 p.m.) Review request for Default. Repository: gem5

Re: [gem5-dev] pd-gem5: simulating a parallel/distributed system on multiple physical hosts

Thanks for the example, I can see your point. Indeed, a gem5 process can miss a receive tick when we restore from a checkpoint with a smaller link latency but this can only happen while that particular gem5 is blocked waiting for the very first periodic sync to complete. This is already handled as

[gem5-dev] Review Request 2950: dev, arm: Rewrite the HDLCD controller

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2950/ --- Review request for Default. Repository: gem5 Description --- Changeset 10925

[gem5-dev] Review Request 2949: dev: Implement a simple display timing generator

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2949/ --- Review request for Default. Repository: gem5 Description --- Changeset 10924

[gem5-dev] Review Request 2948: dev, x86: Fix serialization bug in the i8042 device

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2948/ --- Review request for Default. Repository: gem5 Description --- Changeset 10919

Re: [gem5-dev] Review Request 2933: mem: minor change in the XBar class

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2933/ --- (Updated July 8, 2015, 10:41 a.m.) Review request for Default. Repository: gem5

Re: [gem5-dev] Review Request 2936: config: composing a single HMC device

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2936/ --- (Updated July 8, 2015, 10:17 a.m.) Review request for Default. Changes --- S

[gem5-dev] Cron /z/m5/regression/do-regression quick

* build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic passed. * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing passed. * build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing passed. * build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/sim

Re: [gem5-dev] Review Request 2932: mem: minor fixes in the HMC vault model

> On July 1, 2015, 3:07 p.m., Andreas Hansson wrote: > > src/mem/DRAMCtrl.py, line 460 > > > > > > Really? I was under the impression that the vault controllers were > > simple closed page. See for example > > http://ieeex

Re: [gem5-dev] Review Request 2935: mem: a serial link model for the HMC

--- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2935/ --- (Updated July 8, 2015, 7:42 a.m.) Review request for Default. Changes --- I

Re: [gem5-dev] Review Request 2935: mem: a serial link model for the HMC

> On July 1, 2015, 3:19 p.m., Andreas Hansson wrote: > > src/mem/SerialLink.py, line 60 > > > > > > Do we also need lane width? Lane signalling rate? > > > > No need to add right now, merely wondering if we should no