*
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/minor-timing:
CHANGED!
*
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-timing:
CHANGED!
*
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64i/simple-timing-ruby:
CHANGED!
* build/ALPH
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(Updated Dec. 10, 2016, 10:31 a.m.)
Review request for Default.
Repository: gem5
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(Updated Dez. 10, 2016, 10:33 vorm.)
Review request for Default.
Summary (updated
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Review request for Default.
Repository: gem5
Description
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Changeset 11762
Hi folks,
Yesterday I submitted five patches to the review board. The idea of the
patches is to implement a proper vector register file. To enable cleaner
implementations of the SIMD ISAs.
The first patch extends what Nathanael Premillieu did in spring, taking the
hierarchical RegIds, and