* build/RISCV/tests/opt/quick/se/00.hello/riscv/linux/minor-timing: FAILED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/o3-timing:
FAILED!
*** diff[simout]: SKIPPED*
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64a/minor-timing:
FAILED!
* build/RISC
Hi all,
I ran into a problem today involving an incorrectly decoded AVX
instruction. Hoping someone can tell me of a workaround or a quick fix
other than disabling AVX (unless that's the only solution).
Here's a basic testcase.
int main() {
float x;
__asm__("vxorps %0, %0, %0" : "=x"(x) : "
Hey Sam,
I've got some bad news... I don't think we've implemented any of the AVX
instructions in gem5. In fact, many of the SSE instructions are still
unimplemented.
Overall, the SIMD support for x86 is pretty awful, as of the last time I
checked (some can correct me if things have changed signi
Ah, I see...I noticed a few commits involving decoding of VEX-prefix
instructions and so I assumed that AVX was supported. Or is the problem
that the decoding is supported to some degree but the actual execution
hasn't been implemented?
For what I need to do at the moment, not having good x86 SIMD
Actually, I remember implementing most if not all of SSE of some particular
vintage, so those should work just fine. I even used a test program QEMU
has to do some small amount of verification! :-) But unfortunately I think
you're right that the AVX instructions which aren't also SSE instructions
a
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/5281
Change subject: x86: Fix VEX instruction decoding.
..
x86: Fix VEX instruction decoding.
When decoding VEX prefixed instructions, th
https://gem5-review.googlesource.com/c/public/gem5/+/5281
On Fri, Oct 27, 2017 at 1:18 PM, Gabe Black wrote:
> Actually, I remember implementing most if not all of SSE of some
> particular vintage, so those should work just fine. I even used a test
> program QEMU has to do some small amount of v
