*
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/minor-timing:
FAILED!
* build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/o3-timing:
FAILED!
*** diff[simerr]: SKIPPED*
build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64c/simple-timing:
FAILED!
Hello Jason Lowe-Power, Nikos Nikoleris,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/11412
to look at the new patch set (#7).
Change subject: mem-cache: Create BDI Compressor
.
Hello Jason Lowe-Power, Nikos Nikoleris,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/11411
to look at the new patch set (#7).
Change subject: mem-cache: Add co-allocation function to compressed tags
.
Hello Jason Lowe-Power, Nikos Nikoleris,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/12087
to look at the new patch set (#4).
Change subject: mem-cache: Handle data expansion
.
Hello Jason Lowe-Power, Nikos Nikoleris,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/11105
to look at the new patch set (#9).
Change subject: mem-cache: Create CPack compressor
...
Hi Gabe,
If I remember correctly, we switched from int regs to cc regs in the
Arm ISA back in 2014 for the same reason as AMD. I.e., to get a separate
register pool in the O3 CPU when renaming. We have similar renaming
issues issues for vector registers, which is why we introduced the new
vector
Giacomo Travaglini has uploaded a new patch set (#2) to the change
originally created by Giacomo Gabrielli. (
https://gem5-review.googlesource.com/c/public/gem5/+/13516 )
Change subject: cpu-o3: O3 LSQ Generalisation
..
cpu-
Giacomo Travaglini has uploaded a new patch set (#8) to the change
originally created by Giacomo Gabrielli. (
https://gem5-review.googlesource.com/c/public/gem5/+/13127 )
Change subject: base: Iterable CircularQueue implementation
..
Giacomo Travaglini has uploaded a new patch set (#8) to the change
originally created by Giacomo Gabrielli. (
https://gem5-review.googlesource.com/c/public/gem5/+/13128 )
Change subject: base: Ported circlebuf to CircularQueue
..
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/13555
Change subject: dev-arm: Fix Gicv2 distributor group register
..
dev-arm: Fix Gicv2 distributor group regist
Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/13556
Change subject: dev-arm: Don't panic when EOIR a non active PPI
..
dev-arm: Don't panic when EOIR a non acti
Giacomo Travaglini has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/13556 )
Change subject: dev-arm: Don't panic when EOIR a non active PPI
..
dev-arm: Don't panic when EOIR a
Giacomo Travaglini has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/13555 )
Change subject: dev-arm: Fix Gicv2 distributor group register
..
dev-arm: Fix Gicv2 distributor gro
Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/13539 )
Change subject: arch: Get rid of the unused type AnyReg.
..
arch: Get rid of the unused type AnyReg.
This
Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/13468 )
Change subject: dev: Build the PCI device models even in NULL_ISA builds.
..
dev: Build the PCI device mode
Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/13469 )
Change subject: dev: Build most of the networking devices in the NULL_ISA
build.
..
dev: Build most of t
Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/13470 )
Change subject: python: Stop conditionally excluding code from pyobject.cc
..
python: Stop conditionally ex
Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/13462 )
Change subject: dev: Explicitly specify the endianness for packet accessors.
..
dev: Explicitly specify the
Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/13537 )
Change subject: dev: Remove using namespace TheISA in uart8250.cc.
..
dev: Remove using namespace TheISA in
Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/13538 )
Change subject: arch: Include some additional headers in
arch/generic/mmapped_ipr.cc.
..
arch: Include s
Yes, the CC registers should both not be a single logical register (I don't
think they ever were in x86? can't remember for sure) to avoid false
dependencies between unrelated sets of bits, and they shouldn't be a single
physical register and should be renamed.
I see what you're saying about havin
Hi Andreas,
Good question. I don't see any reason why we couldn't reverse the order in
simulate.py (
https://gem5.googlesource.com/public/gem5/+/master/src/python/m5/simulate.py#155).
TBH, I'm not sure it's really appropriate to have the stats dump like that
anyway. I'd rather see explicit calls v
Hello Jason Lowe-Power, Alec Roelke, Andreas Sandberg,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/13466
to look at the new patch set (#3).
Change subject: null: Stop specifying an endianness in isa_traits.hh.
..
Hello Anthony Gutierrez, Jason Lowe-Power, Alec Roelke, Andreas Sandberg,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/13463
to look at the new patch set (#3).
Change subject: gpu-compute: Explicitly use little endian packet accessor
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/13575
Change subject: mem: Mark the guest endianness packet accessors as
deprecated.
..
mem: Mark the guest endianness
Hello Jason Lowe-Power, Alec Roelke, Andreas Sandberg,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/13465
to look at the new patch set (#3).
Change subject: mem: Delete the packet accessors which use guest endianness.
...
Hello Jason Lowe-Power, Nikos Nikoleris, Alec Roelke, Andreas Sandberg,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/13464
to look at the new patch set (#3).
Change subject: mem: Explicitly specify the endianness in the abstract
me
Gabe Black has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/13463 )
Change subject: gpu-compute: Explicitly use little endian packet accessors.
..
gpu-compute: Explicitly use
Hello Jason Lowe-Power, Alec Roelke, Andreas Sandberg,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/13465
to look at the new patch set (#4).
Change subject: mem: Delete the packet accessors which use guest endianness.
...
Hello Jason Lowe-Power, Alec Roelke, Andreas Sandberg,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/13575
to look at the new patch set (#2).
Change subject: mem: Mark the guest endianness packet accessors as
deprecated.
..
To avoid having to sign into github or writing a big comment on an only
semi-related CL, I'll put this in an email. I did some digging and I think
I know what the problem is from and why your patch fixes it, based on my
reading of gem5 and the kernel's source.
First, the guest tries to do a mov fr
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