Hello Gabor Dozsa,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/19171
to look at the new patch set (#2).
Change subject: arch-arm: Fix tracing code for SVE gather
..
Hello Gabor Dozsa,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/19172
to look at the new patch set (#2).
Change subject: arch-arm: Fix reg dependency for SVE gather microops
...
Hello Adria Armejach, Giacomo Travaglini,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/19169
to look at the new patch set (#2).
Change subject: arch-arm: Fix decoding for SVE memory instructions
..
Hello Gabor Dozsa,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/19176
to review the following change.
Change subject: sim: Add getter to fault virtual address
..
sim
Hello Gabor Dozsa,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/19173
to look at the new patch set (#2).
Change subject: cpu: Disable value forwarding for stores with write strobes
Hello Javier,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/19170
to look at the new patch set (#2).
Change subject: arch-arm: Add SVE LD1RQ[BHWD]
..
arch-arm: Add S
Hello Gabor Dozsa,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/19178
to review the following change.
Change subject: cpu: Add first-/non-faulting load support to Minor and O3
..
Hello Gabor Dozsa,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/19175
to look at the new patch set (#2).
Change subject: cpu: Fix the type of the effective mem request size
Hello Gabor Dozsa,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/19174
to look at the new patch set (#2).
Change subject: cpu-o3: Fix too strict assert condition in writeback()
.
Hello Gabor Dozsa,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/19177
to review the following change.
Change subject: arch-arm: Add first-/non-faulting load instructions
* build/NULL/tests/opt/quick/se/80.dram-closepage/null/none/dram-lowp:
FAILED!
* build/NULL/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby: FAILED!
* build/NULL/tests/opt/quick/se/80.dram-openpage/null/none/dram-lowp:
FAILED!
*
build/NULL_MOESI_hammer/tests/opt/quick/se/6
Tiago Mück has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/18417 )
Change subject: cpu: Limit TrafficGen outstanding reqs
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cpu: Limit TrafficGen outstanding reqs
Parameter
Tiago Mück has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/18416 )
Change subject: cpu: TrafficGen as BaseCPU
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cpu: TrafficGen as BaseCPU
TrafficGen has additional attribu
Tiago Mück has submitted this change and it was merged. (
https://gem5-review.googlesource.com/c/public/gem5/+/18418 )
Change subject: cpu: Additional TrafficGen stats
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cpu: Additional TrafficGen stats
Additional stats to k
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