[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix Trap to EL1 on register DC CVAU

Jordi Vaquero has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/31774 ) Change subject: arch-arm: Fix Trap to EL1 on register DC CVAU .. arch-arm: Fix Trap to EL1 on register DC CVAU

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix Trap to EL1 on register DC CVAU

Jordi Vaquero has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/31774 ) Change subject: arch-arm: Fix Trap to EL1 on register DC CVAU .. arch-arm: Fix Trap to EL1 on register DC CVAU Change-Id:

[gem5-dev] Change in gem5/gem5[develop]: dev-arm: Fix _CTL_EL.ISTATUS when masking the irq

Hello Andreas Sandberg, Adrian Herrera, I'd like you to do a code review. Please visit https://gem5-review.googlesource.com/c/public/gem5/+/31775 to review the following change. Change subject: dev-arm: Fix _CTL_EL.ISTATUS when masking the irq .

[gem5-dev] Can the MESI_Three_Level protocol be used in the L1-L2-L3 three-level cache?

I have some questions about MESI_Three_Level protocol in gem5； First: In options.py, there is no --l3caches in "cache options", but there is --l3_size and --l3_assoc, and I do not know how to add L3 cache in Ruby when I use MESI_Three_Level protocol ? Second, the MESI_Three_Level protocol, It

[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Getter/setter for atomic ops in WriteMask

Matthew Poremba has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/31474 ) Change subject: mem-ruby: Getter/setter for atomic ops in WriteMask .. mem-ruby: Getter/setter for atomic ops in WriteMa

[gem5-dev] Change in gem5/gem5[develop]: util: Update HIP patch used in gcn Dockerfile

Kyle Roarty has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/31794 ) Change subject: util: Update HIP patch used in gcn Dockerfile .. util: Update HIP patch used in gcn Dockerfile T

[gem5-dev] Change in gem5/gem5[develop]: base,sim,python: Add core python API

Jason Lowe-Power has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/31756 ) Change subject: base,sim,python: Add core python API .. base,sim,python: Add core python API Add documenati

[gem5-dev] Ticks to Cycles

Hello Everyone, How can I convert ticks to cycles for the CPU, GPU, Memory, Garnet NoC etc. How are these values set in Gem5 ? Thank you, John Domingo Virus-free. www.avast

[gem5-dev] Re: Ticks to Cycles

Hi John, The clock domain object should do this conversion for you. If you set a clock to 1 GHz, then when you use "Cycle" in that object it will be converted to 1000 ticks (assuming then normal tick rate of 1ps). Most objects are a "ClockedObject" Cheers, Jason On Fri, Jul 24, 2020 at 2:41 PM J

[gem5-dev] Re: Ticks to Cycles

Hi Jason, If I look at the config.json, I see "clk_domain->clock" under it. To manually calculate the number of cycles, can I divide the number of ticks by this value ? Thank you, John Domingo

[gem5-dev] Re: Ticks to Cycles

Hi John, Yeah, that would work! In the c++ code you can also use the Cycle() object. Cheers, Jason On Fri, Jul 24, 2020 at 3:17 PM John Domingo wrote: > Hi Jason, > > If I look at the config.json, I see "clk_domain->clock" under it. > To manually calculate the number of cycles, can I divide th

[gem5-dev] Re: Ticks to Cycles

I need to carryout some manual stat verification. This was very helpful Thanks Jason. Virus-free. www.avast.com