[gem5-dev] Change in gem5/gem5[develop]: x86: Set the effective base of the TSS when initializing a process.

Gabe Black has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/38488 ) Change subject: x86: Set the effective base of the TSS when initializing a process. .. x86: Set the effective base of the

[gem5-dev] Change in gem5/gem5[develop]: x86: Fix some comments in x86 KVM process initialization.

Gabe Black has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/38537 ) Change subject: x86: Fix some comments in x86 KVM process initialization. .. x86: Fix some comments in x86 KVM pro

[gem5-dev] Change in gem5/gem5[develop]: x86: Use the right register type when initializing x86 kvm processes.

Gabe Black has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/38535 ) Change subject: x86: Use the right register type when initializing x86 kvm processes. .. x86: Use the right reg

[gem5-dev] Change in gem5/gem5[develop]: x86: Change some CR0 settings when setting up kvm x86 processes.

Gabe Black has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/38536 ) Change subject: x86: Change some CR0 settings when setting up kvm x86 processes. .. x86: Change some CR0 settin

[gem5-dev] Change in gem5/gem5[develop]: x86: Some small style fixes in arch/x86/process.hh.

Gabe Black has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/38489 ) Change subject: x86: Some small style fixes in arch/x86/process.hh. .. x86: Some small style fixes in arch/x86/process.hh. M

[gem5-dev] Re: CPU/thread context capabilitiy/feature bits

You make a good point, this does have some connection to the ARM system/ISA objects and the configuration they manage. That had crossed my mind, but since I came at this from a different direction I wasn't thinking of doing something about that directly here. I definitely agree that how the ARM sys

[gem5-dev] Re: CPU/thread context capabilitiy/feature bits

Hi Gabe, Let me first say that I like what you are trying to do. Are you thinking about changing the querying interface only, or are you thinking about restructuring the back-end as well? Like where ISA specific parameters are actually stored? For example in Arm we have system level properties

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv,util: Add m5op.S for riscv to enable pseudo inst use

Ayaz Akram has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/38515 ) Change subject: arch-riscv,util: Add m5op.S for riscv to enable pseudo inst use .. arch-riscv,util: Add m5op.S