[gem5-dev] Change in gem5/gem5[develop]: mem-ruby: Memory range configuration for NUMA system

Daecheol You has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/56610 ) Change subject: mem-ruby: Memory range configuration for NUMA system .. mem-ruby: Memory range configuration for

[gem5-dev] Change in gem5/gem5[develop]: python: Update gem5 url output by the simulator

Bobby Bruce has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/56649 ) Change subject: python: Update gem5 url output by the simulator .. python: Update gem5 url output by the simulato

[gem5-dev] Change in gem5/gem5[develop]: tests: Add x86 mutlicore boot tests for timing CPUs

Bobby Bruce has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/55744 ) Change subject: tests: Add x86 mutlicore boot tests for timing CPUs .. tests: Add x86 mutlicore boot tests for timing CPUs

[gem5-dev] Change in gem5/gem5[develop]: mem-cache,tests: Add unit test for ReplaceableEntry

Daniel Carvalho has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/44110 ) ( 12 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mem-cache,tests: Add unit test for Replaceab

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add helper MISCREG to track a pending DVM operation

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/56601 ) Change subject: arch-arm: Add helper MISCREG to track a pending DVM operation .. arch-arm: Add helper M

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implement DSB Shareable as a DVM op

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/56607 ) Change subject: arch-arm: Implement DSB Shareable as a DVM op .. arch-arm: Implement DSB Shareable as a DV

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add DVM enabled flag in the ExtMachInst/Decoder class

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/56603 ) Change subject: arch-arm: Add DVM enabled flag in the ExtMachInst/Decoder class .. arch-arm: Add DVM en

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Create a magic PendingDvm operand

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/56602 ) Change subject: arch-arm: Create a magic PendingDvm operand .. arch-arm: Create a magic PendingDvm operand

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implement TLBI Shareable as a DVM op

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/56606 ) Change subject: arch-arm: Implement TLBI Shareable as a DVM op .. arch-arm: Implement TLBI Shareable as a

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add DVM ISA templates

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/56604 ) Change subject: arch-arm: Add DVM ISA templates .. arch-arm: Add DVM ISA templates These will be used by

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Add warning when DVM is enabled in the decoder

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/56605 ) Change subject: arch-arm: Add warning when DVM is enabled in the decoder .. arch-arm: Add warning when DVM

[gem5-dev] Change in gem5/gem5[develop]: cpu: Allow TLB shootdown requests in the timing cpu

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/56599 ) Change subject: cpu: Allow TLB shootdown requests in the timing cpu .. cpu: Allow TLB shootdown requests i

[gem5-dev] Change in gem5/gem5[develop]: cpu: Rename initiateHtmCmd to be more generic

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/56598 ) Change subject: cpu: Rename initiateHtmCmd to be more generic .. cpu: Rename initiateHtmCmd to be more gen

[gem5-dev] Change in gem5/gem5[develop]: cpu: Handle Request::NO_ACCESS flag in MinorCPU and O3CPU

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/56591 ) Change subject: cpu: Handle Request::NO_ACCESS flag in MinorCPU and O3CPU .. cpu: Handle Request::NO_ACCES

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Replace mcrMrc15TrapToHyp with mcrMrc15Trap

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/56592 ) Change subject: arch-arm: Replace mcrMrc15TrapToHyp with mcrMrc15Trap .. arch-arm: Replace mcrMrc15TrapToH

[gem5-dev] Change in gem5/gem5[develop]: cpu: Allow TLB shootdown requests in the o3 cpu

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/56600 ) Change subject: cpu: Allow TLB shootdown requests in the o3 cpu .. cpu: Allow TLB shootdown requests in th

[gem5-dev] Change in gem5/gem5[develop]: cpu: Fix SimpleExecContext coding style

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/56597 ) Change subject: cpu: Fix SimpleExecContext coding style .. cpu: Fix SimpleExecContext coding style JIRA:

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Implement DSB Shareable with a separate class

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/56594 ) Change subject: arch-arm: Implement DSB Shareable with a separate class .. arch-arm: Implement DSB Shareab

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Reuse MCR15 trapping code in DC instructions

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/56593 ) Change subject: arch-arm: Reuse MCR15 trapping code in DC instructions .. arch-arm: Reuse MCR15 trapping c

[gem5-dev] Change in gem5/gem5[develop]: mem: Add TLB invalidation flags to the Request object

Giacomo Travaglini has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/56596 ) Change subject: mem: Add TLB invalidation flags to the Request object .. mem: Add TLB invalidation flags t

[gem5-dev] Change in gem5/gem5[develop]: sim,tests: Add a tag for drain-related files

Daniel Carvalho has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/44108 ) Change subject: sim,tests: Add a tag for drain-related files .. sim,tests: Add a tag for drain-related files This tag c

[gem5-dev] Change in gem5/gem5[develop]: sim,tests: Add unit test for Globals

Daniel Carvalho has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/43593 ) Change subject: sim,tests: Add unit test for Globals .. sim,tests: Add unit test for Globals Add a unit test for sim/gl

[gem5-dev] Change in gem5/gem5[develop]: sim,tests: Add a tag for gem5 events

Daniel Carvalho has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/44107 ) Change subject: sim,tests: Add a tag for gem5 events .. sim,tests: Add a tag for gem5 events This tag can be used to de

[gem5-dev] Change in gem5/gem5[develop]: arch-riscv: fix memory leak problem in page table walker

Luming Wang has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/56609 ) Change subject: arch-riscv: fix memory leak problem in page table walker .. arch-riscv: fix memory leak problem i