changeset c5a2c5ef6e68 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=c5a2c5ef6e68
description:
minor: fixed LSQ MasterPortID
Minor was reporting the data cache access as ".inst" accesses.
This just switches the MasterPortID to dataMasterPortId.
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Repository: gem5
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Changeset 10540
changeset d0c2ba70dc12 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=d0c2ba70dc12
description:
cpu: Minor Draining Bug
Fixes a bug where Minor drains in the midst of committing a
conditional store.
While committing a conditional store, lastC
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(Updated Oct. 29, 2014, 3:01 p.m.)
Review request for Default.
Repository: gem5
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(Updated Oct. 29, 2014, 3:01 p.m.)
Review request for Default.
Repository: gem5
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Repository: gem5
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Changeset 10510
changeset 933cc91f63e1 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=933cc91f63e1
description:
cpu: Fix o3 SMT IQCount bug
Commmitted by: Nilay Vaish
diffstat:
src/cpu/o3/fetch_impl.hh | 12 ++--
1 files changed, 10 insertions(+), 2 deletions(-)
changeset bdb307e8be54 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=bdb307e8be54
description:
sim: draining bug for fast-forwaring multiple cores
fix draining bug where multiple cores hit max_insts_any_thread
simultaneously
Committed by: Nilay Vais
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(Updated Sept. 15, 2014, 6:29 p.m.)
Review request for Default.
Summary (updated)
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(Updated Sept. 15, 2014, 6:02 p.m.)
Review request for Default.
Summary (updated)
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Repository: gem5
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Changeset 10366
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(Updated May 30, 2014, 2:20 p.m.)
Review request for Default.
Repository: gem5
> On April 30, 2014, 3:13 a.m., Ali Saidi wrote:
> > Thanks for the patch Andrew.
> >
> > My only hesitation is that this does seem to create another issue (probably
> > a less likely one) where the simulator could try to really exit here and
> > fail. That said it's probably good to fix this
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