Once I have more fixes and additions in I'll submit the next PR.
Looking forward to working with you guys to get RVV feature complete and
finally merged into mainline.
Jerin
On Sep 8, 2022 at 16:35:09, Jerin Joy wrote:
> Hi,
>
> Sorry for the late reply. Your email was archived i
andle. But I think that can be done after merging your PR.
>
> Also, we will migrate to GitHub for development considering it’s easier
> for us to work together.
>
> On Sat, Sep 3, 2022 at 6:01 AM Jerin Joy wrote:
>
>> Hi,
>>
>> We want to restart this conver
Hi,
We want to restart this conversation about working on a single RVV
implementation to be merged into upstream Gem5.
We also think adding microcode support for the RVV instructions is the
right way to go.
To get started, we created a fork of PLCT lab’s Gem5 repo and have started
commiting
Hi,
Before diving into details of the code, if there's interest from the
>>> community I can set up a meeting time for us all to get together on zoom to
>>> chat about details and the best way to work together.
>>>
>>
Yes, we at Rivos are also be interested in attending. It would be good if
we
Jerin Joy has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/58631 )
(
3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: arch-riscv: Added the Zbc bitmanip instructions
Jerin Joy has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/58632 )
(
3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: arch-riscv: Added the Zbs bitmanip instructions
Jerin Joy has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/58630 )
Change subject: arch-riscv: Added the Zba and Zbb bitmanip instructions
..
arch-riscv: Added the Zba and Zbb bitmanip
Jerin Joy has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/58630 )
Change subject: arch-riscv: Added the Zba and Zbb bitmanip instructions
..
arch-riscv: Added the Zba and Zbb
Jerin Joy has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/58632 )
Change subject: arch-riscv: Added the Zbs bitmanip instructions
..
arch-riscv: Added the Zbs bitmanip instructions
Jerin Joy has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/58631 )
Change subject: arch-riscv: Added the Zbc bitmanip instructions
..
arch-riscv: Added the Zbc bitmanip instructions
Hi Yang,
We (Rivos) are also looking at adding RVV support to Gem5. I had sent an email
out yesterday about the changes we've released publicly:
https://www.mail-archive.com/gem5-dev@gem5.org/msg42420.html
We could possibly collaborate to get RVV support into mainline Gem5 to avoid
duplication
into mainline Gem5.
Details:
The model builds with:
scons build/RISCV/gem5.opt
I made a few hacks to get things working. I’ve split these out as separate
commits (prefixed with HACK: ) detailed here:
commit d6d068c9fabf34e5327107513ec41dea3e5e9acc
Author: Jerin Joy
Date: Wed Mar 2 11:29:18 2022
I’m adding RISCV Vector extension support in Gem5 and I have a question
about how to load up the source/dest vector registers used by the
instructions.
The ISA parser generates code to load the source and target registers for
an instruction depending on the strings it sees in the code block for
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