[gem5-dev] Question about RISCV Vector register support

I’m adding RISCV Vector extension support in Gem5 and I have a question about how to load up the source/dest vector registers used by the instructions. The ISA parser generates code to load the source and target registers for an instruction depending on the strings it sees in the code block for th

[gem5-dev] Rivos: Initial RVV support

Rivos is working on adding RISC-V Vector support to Gem5. We've pushed the initial set of changes to our public fork here: https://github.com/rivosinc/gem5/commits/rivos/dev/joy/initial_RVV_support We’d like to get feedback from the community and make the changes required to get this merged into m

[gem5-dev] Re: Dynamic number of micro-ops based on misc registers

Hi Yang, We (Rivos) are also looking at adding RVV support to Gem5. I had sent an email out yesterday about the changes we've released publicly: https://www.mail-archive.com/gem5-dev@gem5.org/msg42420.html We could possibly collaborate to get RVV support into mainline Gem5 to avoid duplication