rofessor, Computer Science Department
> University of California, Davis
> 3049 Kemper Hall
> https://faculty.engineering.ucdavis.edu/lowepower/
>
>
>
> On Tue, Dec 12, 2017 at 9:07 PM Sam Xi <liku...@fas.harvard.edu> wrote:
>
> > Hi,
> >
> > I am trying
is available in Python. So if this is all true, then would the best
way to implement this to be precomputing all the register outputs in python
and setting them appropriately in the CPU objects as the caches are
instantiated?
Thanks,
Sam
--
Thanks,
Sam Xi
Harvard University
Computer Science, Ph.D
indly passed to the simulated
> process in gem5. If you're using se.py, it looks like the --env option is
> what you want.
>
> Gabe
>
> On Tue, Dec 12, 2017 at 12:14 PM, Sam Xi <liku...@fas.harvard.edu> wrote:
>
> > Hi all,
> >
> > I'm running into an issue with sim
ce, but not having to do this would be nice.
I'm running on x86, simulating x86 too, on Ubuntu 16.04.
Thanks,
Sam
--
Thanks,
Sam Xi
Harvard University
Computer Science, Ph.D. Candidate
http://www.samxi.org
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Thanks,
Sam Xi
Harvard University
Computer Science, Ph.D. Candidate
http://www.samxi.org
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Oh I see. This particular instruction was also an SSE instruction. Thanks
for the clarification.
On Sun, Oct 29, 2017, 12:02 AM Gabe Black <gabebl...@google.com> wrote:
> As I mentioned before, the instruction is not unimplemented.
>
> Gabe
>
> On Sat, Oct 28, 2017 at
t; properly however, so it's probably worth looking into why this one
> wasn't.
> >
> > Gabe
> >
> > On Fri, Oct 27, 2017 at 1:07 PM, Sam Xi <liku...@fas.harvard.edu> wrote:
> >
> >> Ah, I see...I noticed a few commits involving decoding of VEX-prefix
>
s not pushed out
> yet. Brad, Tony, care to comment?
>
> Sorry this isn't better news. This has been a pain point for me for a
> while, but I haven't had any time to work on it.
>
> Cheers,
> Jason
>
> On Fri, Oct 27, 2017 at 12:38 PM Sam Xi <liku...@fas.harvard.edu> wrote:
&
45d2ec9543c31af55
Thanks,
Sam
--
Thanks,
Sam Xi
Harvard University
Computer Science, Ph.D. Candidate
http://www.samxi.org
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