Wendy Elsasser has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28967 )
Change subject: mem: Factor out DRAM interface
..
mem: Factor out DRAM interface
Separate out the DRAM specif
nst Tick tXP;
const Tick tXS;
+const Tick clkResyncDelay;
+ unsigned int maxCommandsPerBurst;
+const bool dataClockSync;
+const uint8_t twoCycleActivate;
const uint32_t activationLimit;
const Tick rankToRankDly;
const Tick wrToRdDly;
const Tick rdToWrDly;
;
const Tick tXP;
const Tick tXS;
+ const Tick clkResyncDelay;
+const uint8_t maxCommandsPerBurst;
+const bool dataClockSync;
+const uint8_t twoCycleActivate;
const uint32_t activationLimit;
const Tick rankToRankDly;
const Tick wrToRdDly;
const Tick rdToWrDly;
+const Tick wrToRdDlySameBG;
+const Tick rdToWrDlySameBG;
+const bool burstInterleave;
+const Tick burstDataCycles;
/**
* Memory controller configuration initialized based on parameter
diff --git a/src/mem/drampower.cc b/src/mem/drampower.cc
index 0510791..f506928 100644
--- a/src/mem/drampower.cc
+++ b/src/mem/drampower.cc
@@ -150,10 +150,10 @@
uint8_t
DRAMPower::getDataRate(const DRAMCtrlParams* p)
{
-uint32_t burst_cycles = divCeil(p->tBURST, p->tCK);
+uint32_t burst_cycles = divCeil(p->tBURST_MAX, p->tCK);
uint8_t data_rate = p->burst_length / burst_cycles;
// 4 for GDDR5
-if (data_rate != 1 && data_rate != 2 && data_rate != 4)
-fatal("Got unexpected data rate %d, should be 1 or 2 or 4\n");
+if (data_rate != 1 && data_rate != 2 && data_rate != 4 && data_rate !=
8)
+fatal("Got unexpected data rate %d, should be 1 or 2 or 4 or 8\n");
return data_rate;
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I1b14fed221350e6e403f7cbf089fe6c7f033c181
Gerrit-Change-Number: 26236
Gerrit-PatchSet: 1
Gerrit-Owner: Wendy Elsasser
Gerrit-MessageType: newchange
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