Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/34175 )
Change subject: arch: Report the page size from the TLB.
......................................................................
arch: Report the page size from the TLB.
The TLB knows what the (a?) page size is for its architecture. Make that
queriable. Really there are usually multiple page sizes so this isn't a
very accurate way to do things, but it's consistent with the existing
mechanism.
Change-Id: I0f3afdf6a3db7bfad12accfd90c6edb183c20c8f
---
M src/arch/arm/fastmodel/iris/tlb.hh
M src/arch/arm/tlb.hh
M src/arch/generic/tlb.hh
M src/arch/mips/tlb.hh
M src/arch/power/tlb.hh
M src/arch/riscv/tlb.hh
M src/arch/sparc/tlb.hh
M src/arch/x86/tlb.hh
M src/sim/process.cc
9 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/src/arch/arm/fastmodel/iris/tlb.hh
b/src/arch/arm/fastmodel/iris/tlb.hh
index 1d9c216..1f7caed 100644
--- a/src/arch/arm/fastmodel/iris/tlb.hh
+++ b/src/arch/arm/fastmodel/iris/tlb.hh
@@ -28,6 +28,7 @@
#ifndef __ARCH_ARM_FASTMODEL_IRIS_TLB_HH__
#define __ARCH_ARM_FASTMODEL_IRIS_TLB_HH__
+#include "arch/arm/system.hh"
#include "arch/generic/tlb.hh"
namespace Iris
@@ -38,6 +39,8 @@
public:
TLB(const Params *p) : BaseTLB(p) {}
+ Addr pageShift() const override { return ArmSystem::PageShift; }
+
void demapPage(Addr vaddr, uint64_t asn) override {}
void flushAll() override {}
void takeOverFrom(BaseTLB *otlb) override {}
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index 004ce0b..fc96ca7 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -45,6 +45,7 @@
#include "arch/arm/faults.hh"
#include "arch/arm/isa_traits.hh"
#include "arch/arm/pagetable.hh"
+#include "arch/arm/system.hh"
#include "arch/arm/utility.hh"
#include "arch/generic/tlb.hh"
#include "base/statistics.hh"
@@ -215,6 +216,8 @@
virtual ~TLB();
+ Addr pageShift() const override { return ArmSystem::PageShift; }
+
void takeOverFrom(BaseTLB *otlb) override;
/// setup all the back pointers
diff --git a/src/arch/generic/tlb.hh b/src/arch/generic/tlb.hh
index f144f69..0c5b8e2 100644
--- a/src/arch/generic/tlb.hh
+++ b/src/arch/generic/tlb.hh
@@ -85,6 +85,12 @@
};
public:
+ virtual Addr pageShift() const = 0;
+ Addr pageSize() const { return 0x1ULL << pageShift(); }
+ Addr pageOffset(Addr a) const { return a & (pageSize() - 1); }
+ Addr pageAlign(Addr a) const { return a & ~(pageSize() - 1); }
+ Addr pageAlignUp(Addr a) const { return pageAlign(a + pageSize() - 1);
}
+
virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
virtual Fault translateAtomic(
diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh
index 2be2ddf..d9f6d42 100644
--- a/src/arch/mips/tlb.hh
+++ b/src/arch/mips/tlb.hh
@@ -69,6 +69,8 @@
MipsISA::PTE *getEntry(unsigned) const;
virtual ~TLB();
+ Addr pageShift() const override { return PageShift; }
+
void takeOverFrom(BaseTLB *otlb) override {}
int smallPages;
diff --git a/src/arch/power/tlb.hh b/src/arch/power/tlb.hh
index c119d93..954ff07 100644
--- a/src/arch/power/tlb.hh
+++ b/src/arch/power/tlb.hh
@@ -115,6 +115,8 @@
TLB(const Params *p);
virtual ~TLB();
+ Addr pageShift() const override { return PageShift; }
+
void takeOverFrom(BaseTLB *otlb) override {}
int probeEntry(Addr vpn,uint8_t) const;
diff --git a/src/arch/riscv/tlb.hh b/src/arch/riscv/tlb.hh
index a92bdd2..060cc53 100644
--- a/src/arch/riscv/tlb.hh
+++ b/src/arch/riscv/tlb.hh
@@ -87,6 +87,8 @@
Walker *getWalker();
+ Addr pageShift() const override { return PageShift; }
+
void takeOverFrom(BaseTLB *otlb) override {}
TlbEntry *insert(Addr vpn, const TlbEntry &entry);
diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index 15333ab..df5ce64 100644
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -156,6 +156,8 @@
typedef SparcTLBParams Params;
TLB(const Params *p);
+ Addr pageShift() const override { return PageShift; }
+
void takeOverFrom(BaseTLB *otlb) override {}
void
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index 671b165..1547bbc 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -68,6 +68,8 @@
typedef X86TLBParams Params;
TLB(const Params *p);
+ Addr pageShift() const override { return PageShift; }
+
void takeOverFrom(BaseTLB *otlb) override {}
TlbEntry *lookup(Addr va, bool update_lru = true);
diff --git a/src/sim/process.cc b/src/sim/process.cc
index 88277ee..e46ff7d 100644
--- a/src/sim/process.cc
+++ b/src/sim/process.cc
@@ -318,7 +318,7 @@
void
Process::allocateMem(Addr vaddr, int64_t size, bool clobber)
{
- int npages = divCeil(size, pTable->pageSize();
+ int npages = divCeil(size, pTable->pageSize());
Addr paddr = system->allocPhysPages(npages);
pTable->map(vaddr, paddr, size,
clobber ? EmulationPageTable::Clobber :
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I0f3afdf6a3db7bfad12accfd90c6edb183c20c8f
Gerrit-Change-Number: 34175
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabebl...@google.com>
Gerrit-MessageType: newchange
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