Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/49144 )
Change subject: arch-arm: Fix style in utility.hh.
......................................................................
arch-arm: Fix style in utility.hh.
Change-Id: I66262e63695680f5638ef057be05274445ba38ac
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49144
Maintainer: Bobby R. Bruce <bbr...@ucdavis.edu>
Tested-by: kokoro <noreply+kok...@google.com>
Reviewed-by: Gabe Black <gabe.bl...@gmail.com>
---
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
2 files changed, 149 insertions(+), 173 deletions(-)
Approvals:
Gabe Black: Looks good to me, approved
Bobby R. Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index bd1af44..b716ba9 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -305,7 +305,7 @@
std::pair<bool, bool>
ELUsingAArch32K(ThreadContext *tc, ExceptionLevel el)
{
- bool secure = isSecureBelowEL3(tc);
+ bool secure = isSecureBelowEL3(tc);
return ELStateUsingAArch32K(tc, el, secure);
}
@@ -366,8 +366,8 @@
aarch32 = (cpsr.width == 1);
} else {
known = true;
- aarch32 = (aarch32_below_el3 && el != EL3)
- || (aarch32_at_el1 && (el == EL0 || el == EL1) );
+ aarch32 = (aarch32_below_el3 && el != EL3) ||
+ (aarch32_at_el1 && (el == EL0 || el == EL1) );
}
}
@@ -510,13 +510,13 @@
mcrMrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc, uint32_t
iss,
ExceptionClass *ec)
{
- bool isRead;
- uint32_t crm;
+ bool isRead;
+ uint32_t crm;
IntRegIndex rt;
- uint32_t crn;
- uint32_t opc1;
- uint32_t opc2;
- bool trapToHype = false;
+ uint32_t crn;
+ uint32_t opc1;
+ uint32_t opc2;
+ bool trapToHype = false;
const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
const HCR hcr = tc->readMiscReg(MISCREG_HCR);
@@ -531,8 +531,8 @@
trapToHype |= hdcr.tpm && (crn == 9) && (crm >= 12);
trapToHype |= hcr.tidcp && (
((crn == 9) && ((crm <= 2) || ((crm >= 5) && (crm <= 8)))) ||
- ((crn == 10) && ((crm <= 1) || (crm == 4) || (crm == 8))) ||
- ((crn == 11) && ((crm <= 8) || (crm == 15))) );
+ ((crn == 10) && ((crm <= 1) || (crm == 4) || (crm == 8))) ||
+ ((crn == 11) && ((crm <= 8) || (crm == 15))));
if (!trapToHype) {
switch (unflattenMiscReg(miscReg)) {
@@ -667,13 +667,13 @@
mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss)
{
- bool isRead;
- uint32_t crm;
+ bool isRead;
+ uint32_t crm;
IntRegIndex rt;
- uint32_t crn;
- uint32_t opc1;
- uint32_t opc2;
- bool trapToHype = false;
+ uint32_t crn;
+ uint32_t opc1;
+ uint32_t opc2;
+ bool trapToHype = false;
if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) {
mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
@@ -727,13 +727,13 @@
mcrrMrrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc,
uint32_t iss, ExceptionClass *ec)
{
- uint32_t crm;
+ uint32_t crm;
IntRegIndex rt;
- uint32_t crn;
- uint32_t opc1;
- uint32_t opc2;
- bool isRead;
- bool trapToHype = false;
+ uint32_t crn;
+ uint32_t opc1;
+ uint32_t opc2;
+ bool isRead;
+ bool trapToHype = false;
const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
const HCR hcr = tc->readMiscReg(MISCREG_HCR);
@@ -745,7 +745,7 @@
// the moment because we only need one field, which overlaps with
the
// mcrmrc layout
mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2);
- trapToHype = ((uint32_t) hstr) & (1 << crm);
+ trapToHype = ((uint32_t)hstr) & (1 << crm);
if (!trapToHype) {
switch (unflattenMiscReg(miscReg)) {
@@ -771,8 +771,9 @@
// CNTFRQ may be trapped only on reads
// CNTPCT and CNTVCT are read-only
if (MISCREG_CNTFRQ <= miscReg && miscReg <= MISCREG_CNTVCT
&&
- !isRead)
+ !isRead) {
break;
+ }
trapToHype = isGenericTimerHypTrap(miscReg, tc, ec);
break;
// No default action needed
@@ -989,8 +990,8 @@
{
const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
bool trap_cond_0 = condGenericTimerPhysEL1SystemAccessTrapEL2(miscReg,
tc);
- bool trap_cond_1 =
condGenericTimerCommonEL1SystemAccessTrapEL2(miscReg,
- tc);
+ bool trap_cond_1 = condGenericTimerCommonEL1SystemAccessTrapEL2(
+ miscReg, tc);
switch (miscReg) {
case MISCREG_CNTPCT:
case MISCREG_CNTPCT_EL0:
@@ -1134,35 +1135,34 @@
isIntReg = !r;
// Loosely based on ARM ARM issue C section B9.3.10
if (r) {
- switch (sysM)
- {
+ switch (sysM) {
case 0xE:
regIdx = MISCREG_SPSR_FIQ;
- mode = MODE_FIQ;
+ mode = MODE_FIQ;
break;
case 0x10:
regIdx = MISCREG_SPSR_IRQ;
- mode = MODE_IRQ;
+ mode = MODE_IRQ;
break;
case 0x12:
regIdx = MISCREG_SPSR_SVC;
- mode = MODE_SVC;
+ mode = MODE_SVC;
break;
case 0x14:
regIdx = MISCREG_SPSR_ABT;
- mode = MODE_ABORT;
+ mode = MODE_ABORT;
break;
case 0x16:
regIdx = MISCREG_SPSR_UND;
- mode = MODE_UNDEFINED;
+ mode = MODE_UNDEFINED;
break;
case 0x1C:
regIdx = MISCREG_SPSR_MON;
- mode = MODE_MON;
+ mode = MODE_MON;
break;
case 0x1E:
regIdx = MISCREG_SPSR_HYP;
- mode = MODE_HYP;
+ mode = MODE_HYP;
break;
default:
ok = false;
@@ -1187,18 +1187,18 @@
regIdx = intRegInMode(mode, 13); // R13 in HYP
} else {
isIntReg = false;
- regIdx = MISCREG_ELR_HYP;
+ regIdx = MISCREG_ELR_HYP;
}
}
} else { // Other Banked registers
int sysM2 = bits(sysM, 2);
int sysM1 = bits(sysM, 1);
- mode = (OperatingMode) ( ((sysM2 || sysM1) << 0) |
- (1 << 1) |
- ((sysM2 && !sysM1) << 2) |
- ((sysM2 && sysM1) << 3) |
- (1 << 4) );
+ mode = (OperatingMode)(((sysM2 || sysM1) << 0) |
+ (1 << 1) |
+ ((sysM2 && !sysM1) << 2) |
+ ((sysM2 && sysM1) << 3) |
+ (1 << 4));
regIdx = intRegInMode(mode, 14 - bits(sysM, 0));
// Don't flatten the register here. This is going to go through
// setIntReg() which will do the flattening
@@ -1208,17 +1208,16 @@
// Check that the requested register is accessable from the current
mode
if (ok && checkSecurity && mode != cpsr.mode) {
- switch (cpsr.mode)
- {
+ switch (cpsr.mode) {
case MODE_USER:
ok = false;
break;
case MODE_FIQ:
- ok &= mode != MODE_HYP;
+ ok &= mode != MODE_HYP;
ok &= (mode != MODE_MON) || !scr.ns;
break;
case MODE_HYP:
- ok &= mode != MODE_MON;
+ ok &= mode != MODE_MON;
ok &= (mode != MODE_FIQ) || !nsacr.rfr;
break;
case MODE_IRQ:
@@ -1226,7 +1225,7 @@
case MODE_ABORT:
case MODE_UNDEFINED:
case MODE_SYSTEM:
- ok &= mode != MODE_HYP;
+ ok &= mode != MODE_HYP;
ok &= (mode != MODE_MON) || !scr.ns;
ok &= (mode != MODE_FIQ) || !nsacr.rfr;
break;
@@ -1238,11 +1237,11 @@
break;
}
}
- return (ok);
+ return ok;
}
bool
-isUnpriviledgeAccess(ThreadContext * tc)
+isUnpriviledgeAccess(ThreadContext *tc)
{
const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
// NV Extension not implemented yet
@@ -1259,17 +1258,17 @@
}
bool
-SPAlignmentCheckEnabled(ThreadContext* tc)
+SPAlignmentCheckEnabled(ThreadContext *tc)
{
ExceptionLevel regime = s1TranslationRegime(tc, currEL(tc));
switch (currEL(tc)) {
case EL3:
- return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL3)).sa;
+ return ((SCTLR)tc->readMiscReg(MISCREG_SCTLR_EL3)).sa;
case EL2:
- return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL2)).sa;
+ return ((SCTLR)tc->readMiscReg(MISCREG_SCTLR_EL2)).sa;
case EL1:
- return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).sa;
+ return ((SCTLR)tc->readMiscReg(MISCREG_SCTLR_EL1)).sa;
case EL0:
{
SCTLR sc = (regime == EL2) ? tc->readMiscReg(MISCREG_SCTLR_EL2):
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 9b2496e..9667d47 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -57,7 +57,8 @@
class ArmSystem;
-namespace ArmISA {
+namespace ArmISA
+{
inline bool
testPredicate(uint32_t nz, uint32_t c, uint32_t v, ConditionCode code)
@@ -65,26 +66,25 @@
bool n = (nz & 0x2);
bool z = (nz & 0x1);
- switch (code)
- {
- case COND_EQ: return z;
- case COND_NE: return !z;
- case COND_CS: return c;
- case COND_CC: return !c;
- case COND_MI: return n;
- case COND_PL: return !n;
- case COND_VS: return v;
- case COND_VC: return !v;
- case COND_HI: return (c && !z);
- case COND_LS: return !(c && !z);
- case COND_GE: return !(n ^ v);
- case COND_LT: return (n ^ v);
- case COND_GT: return !(n ^ v || z);
- case COND_LE: return (n ^ v || z);
- case COND_AL: return true;
- case COND_UC: return true;
- default:
- panic("Unhandled predicate condition: %d\n", code);
+ switch (code) {
+ case COND_EQ: return z;
+ case COND_NE: return !z;
+ case COND_CS: return c;
+ case COND_CC: return !c;
+ case COND_MI: return n;
+ case COND_PL: return !n;
+ case COND_VS: return v;
+ case COND_VC: return !v;
+ case COND_HI: return (c && !z);
+ case COND_LS: return !(c && !z);
+ case COND_GE: return !(n ^ v);
+ case COND_LT: return (n ^ v);
+ case COND_GT: return !(n ^ v || z);
+ case COND_LE: return (n ^ v || z);
+ case COND_AL: return true;
+ case COND_UC: return true;
+ default:
+ panic("Unhandled predicate condition: %d\n", code);
}
}
@@ -149,14 +149,12 @@
* @retval aarch32 is TRUE if the specified Exception level is using
AArch32;
* FALSE otherwise.
*/
-std::pair<bool, bool>
-ELUsingAArch32K(ThreadContext *tc, ExceptionLevel el);
+std::pair<bool, bool> ELUsingAArch32K(ThreadContext *tc, ExceptionLevel
el);
-std::pair<bool, bool>
-ELStateUsingAArch32K(ThreadContext *tc, ExceptionLevel el, bool secure);
+std::pair<bool, bool> ELStateUsingAArch32K(ThreadContext *tc,
+ ExceptionLevel el, bool secure);
-bool
-ELStateUsingAArch32(ThreadContext *tc, ExceptionLevel el, bool secure);
+bool ELStateUsingAArch32(ThreadContext *tc, ExceptionLevel el, bool
secure);
bool ELIs32(ThreadContext *tc, ExceptionLevel el);
@@ -203,7 +201,7 @@
return (uint8_t)it;
}
-ExceptionLevel s1TranslationRegime(ThreadContext* tc, ExceptionLevel el);
+ExceptionLevel s1TranslationRegime(ThreadContext *tc, ExceptionLevel el);
/**
* Removes the tag from tagged addresses if that mode is enabled.
@@ -217,7 +215,7 @@
Addr purifyTaggedAddr(Addr addr, ThreadContext *tc, ExceptionLevel el,
bool isInstr);
int computeAddrTop(ThreadContext *tc, bool selbit, bool isInstr,
- TCR tcr, ExceptionLevel el);
+ TCR tcr, ExceptionLevel el);
static inline bool
inSecureState(SCR scr, CPSR cpsr)
@@ -255,35 +253,35 @@
mcrMrcIssBuild(bool isRead, uint32_t crm, IntRegIndex rt, uint32_t crn,
uint32_t opc1, uint32_t opc2)
{
- return (isRead << 0) |
- (crm << 1) |
- (rt << 5) |
- (crn << 10) |
- (opc1 << 14) |
- (opc2 << 17);
+ return (isRead << 0) |
+ (crm << 1) |
+ (rt << 5) |
+ (crn << 10) |
+ (opc1 << 14) |
+ (opc2 << 17);
}
static inline void
mcrMrcIssExtract(uint32_t iss, bool &isRead, uint32_t &crm, IntRegIndex
&rt,
uint32_t &crn, uint32_t &opc1, uint32_t &opc2)
{
- isRead = (iss >> 0) & 0x1;
- crm = (iss >> 1) & 0xF;
- rt = (IntRegIndex) ((iss >> 5) & 0xF);
- crn = (iss >> 10) & 0xF;
- opc1 = (iss >> 14) & 0x7;
- opc2 = (iss >> 17) & 0x7;
+ isRead = (iss >> 0) & 0x1;
+ crm = (iss >> 1) & 0xF;
+ rt = (IntRegIndex)((iss >> 5) & 0xF);
+ crn = (iss >> 10) & 0xF;
+ opc1 = (iss >> 14) & 0x7;
+ opc2 = (iss >> 17) & 0x7;
}
static inline uint32_t
mcrrMrrcIssBuild(bool isRead, uint32_t crm, IntRegIndex rt, IntRegIndex
rt2,
uint32_t opc1)
{
- return (isRead << 0) |
- (crm << 1) |
- (rt << 5) |
- (rt2 << 10) |
- (opc1 << 16);
+ return (isRead << 0) |
+ (crm << 1) |
+ (rt << 5) |
+ (rt2 << 10) |
+ (opc1 << 16);
}
static inline uint32_t
@@ -299,92 +297,69 @@
(op0 << 20);
}
-Fault
-mcrMrc15Trap(const MiscRegIndex miscReg, ExtMachInst machInst,
- ThreadContext *tc, uint32_t imm);
-bool
-mcrMrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc, uint32_t
iss,
- ExceptionClass *ec = nullptr);
+Fault mcrMrc15Trap(const MiscRegIndex miscReg, ExtMachInst machInst,
+ ThreadContext *tc, uint32_t imm);
+bool mcrMrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc,
+ uint32_t iss, ExceptionClass *ec=nullptr);
-bool
-mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
- HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss);
+bool mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR
scr,
+ HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss);
-Fault
-mcrrMrrc15Trap(const MiscRegIndex miscReg, ExtMachInst machInst,
- ThreadContext *tc, uint32_t imm);
-bool
-mcrrMrrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc,
- uint32_t iss, ExceptionClass *ec = nullptr);
+Fault mcrrMrrc15Trap(const MiscRegIndex miscReg, ExtMachInst machInst,
+ ThreadContext *tc, uint32_t imm);
+bool mcrrMrrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc,
+ uint32_t iss, ExceptionClass *ec=nullptr);
-Fault
-AArch64AArch32SystemAccessTrap(const MiscRegIndex miscReg,
- ExtMachInst machInst, ThreadContext *tc,
- uint32_t imm, ExceptionClass ec);
-bool
-isAArch64AArch32SystemAccessTrapEL1(const MiscRegIndex miscReg,
- ThreadContext *tc);
-bool
-isAArch64AArch32SystemAccessTrapEL2(const MiscRegIndex miscReg,
- ThreadContext *tc);
-bool
-isGenericTimerHypTrap(const MiscRegIndex miscReg, ThreadContext *tc,
- ExceptionClass *ec);
+Fault AArch64AArch32SystemAccessTrap(const MiscRegIndex miscReg,
+ ExtMachInst machInst, ThreadContext
*tc,
+ uint32_t imm, ExceptionClass ec);
+bool isAArch64AArch32SystemAccessTrapEL1(const MiscRegIndex miscReg,
+ ThreadContext *tc);
+bool isAArch64AArch32SystemAccessTrapEL2(const MiscRegIndex miscReg,
+ ThreadContext *tc);
+bool isGenericTimerHypTrap(const MiscRegIndex miscReg, ThreadContext *tc,
+ ExceptionClass *ec);
bool condGenericTimerPhysHypTrap(const MiscRegIndex miscReg,
ThreadContext *tc);
-bool
-isGenericTimerCommonEL0HypTrap(const MiscRegIndex miscReg, ThreadContext
*tc,
+bool isGenericTimerCommonEL0HypTrap(const MiscRegIndex miscReg,
+ ThreadContext *tc, ExceptionClass *ec);
+bool isGenericTimerPhysHypTrap(const MiscRegIndex miscReg, ThreadContext
*tc,
ExceptionClass *ec);
-bool
-isGenericTimerPhysHypTrap(const MiscRegIndex miscReg, ThreadContext *tc,
- ExceptionClass *ec);
-bool
-condGenericTimerPhysHypTrap(const MiscRegIndex miscReg, ThreadContext *tc);
-bool
-isGenericTimerSystemAccessTrapEL1(const MiscRegIndex miscReg,
- ThreadContext *tc);
-bool
-condGenericTimerSystemAccessTrapEL1(const MiscRegIndex miscReg,
- ThreadContext *tc);
-bool
-isGenericTimerSystemAccessTrapEL2(const MiscRegIndex miscReg,
- ThreadContext *tc);
-bool
-isGenericTimerCommonEL0SystemAccessTrapEL2(const MiscRegIndex miscReg,
- ThreadContext *tc);
-bool
-isGenericTimerPhysEL0SystemAccessTrapEL2(const MiscRegIndex miscReg,
+bool condGenericTimerPhysHypTrap(const MiscRegIndex miscReg,
+ ThreadContext *tc);
+bool isGenericTimerSystemAccessTrapEL1(const MiscRegIndex miscReg,
+ ThreadContext *tc);
+bool condGenericTimerSystemAccessTrapEL1(const MiscRegIndex miscReg,
ThreadContext *tc);
-bool
-isGenericTimerPhysEL1SystemAccessTrapEL2(const MiscRegIndex miscReg,
- ThreadContext *tc);
-bool
-isGenericTimerVirtSystemAccessTrapEL2(const MiscRegIndex miscReg,
- ThreadContext *tc);
-bool
-condGenericTimerCommonEL0SystemAccessTrapEL2(const MiscRegIndex miscReg,
- ThreadContext *tc);
-bool
-condGenericTimerCommonEL1SystemAccessTrapEL2(const MiscRegIndex miscReg,
- ThreadContext *tc);
-bool
-condGenericTimerPhysEL1SystemAccessTrapEL2(const MiscRegIndex miscReg,
+bool isGenericTimerSystemAccessTrapEL2(const MiscRegIndex miscReg,
+ ThreadContext *tc);
+bool isGenericTimerCommonEL0SystemAccessTrapEL2(const MiscRegIndex miscReg,
+ ThreadContext *tc);
+bool isGenericTimerPhysEL0SystemAccessTrapEL2(const MiscRegIndex miscReg,
+ ThreadContext *tc);
+bool isGenericTimerPhysEL1SystemAccessTrapEL2(const MiscRegIndex miscReg,
+ ThreadContext *tc);
+bool isGenericTimerVirtSystemAccessTrapEL2(const MiscRegIndex miscReg,
ThreadContext *tc);
-bool
-isGenericTimerSystemAccessTrapEL3(const MiscRegIndex miscReg,
- ThreadContext *tc);
+bool condGenericTimerCommonEL0SystemAccessTrapEL2(const MiscRegIndex
miscReg,
+ ThreadContext *tc);
+bool condGenericTimerCommonEL1SystemAccessTrapEL2(const MiscRegIndex
miscReg,
+ ThreadContext *tc);
+bool condGenericTimerPhysEL1SystemAccessTrapEL2(const MiscRegIndex miscReg,
+ ThreadContext *tc);
+bool isGenericTimerSystemAccessTrapEL3(const MiscRegIndex miscReg,
+ ThreadContext *tc);
-bool SPAlignmentCheckEnabled(ThreadContext* tc);
+bool SPAlignmentCheckEnabled(ThreadContext *tc);
Addr truncPage(Addr addr);
Addr roundPage(Addr addr);
// Decodes the register index to access based on the fields used in a MSR
// or MRS instruction
-bool
-decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int ®Idx,
- CPSR cpsr, SCR scr, NSACR nsacr,
- bool checkSecurity = true);
+bool decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int
®Idx,
+ CPSR cpsr, SCR scr, NSACR nsacr,
+ bool checkSecurity=true);
// This wrapper function is used to turn the register index into a source
// parameter for the instruction. See Operands.isa
@@ -395,7 +370,8 @@
bool isIntReg;
bool validReg;
- validReg = decodeMrsMsrBankedReg(sysM, r, isIntReg, regIdx, 0, 0, 0,
false);
+ validReg = decodeMrsMsrBankedReg(
+ sysM, r, isIntReg, regIdx, 0, 0, 0, false);
return (validReg && isIntReg) ? regIdx : INTREG_DUMMY;
}
@@ -409,12 +385,13 @@
*/
uint8_t encodePhysAddrRange64(int pa_size);
-inline ByteOrder byteOrder(const ThreadContext *tc)
+inline ByteOrder
+byteOrder(const ThreadContext *tc)
{
return isBigEndian64(tc) ? ByteOrder::big : ByteOrder::little;
};
-bool isUnpriviledgeAccess(ThreadContext * tc);
+bool isUnpriviledgeAccess(ThreadContext *tc);
} // namespace ArmISA
} // namespace gem5
3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/49144
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I66262e63695680f5638ef057be05274445ba38ac
Gerrit-Change-Number: 49144
Gerrit-PatchSet: 5
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Bobby R. Bruce <bbr...@ucdavis.edu>
Gerrit-Reviewer: Daniel Carvalho <oda...@yahoo.com.br>
Gerrit-Reviewer: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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