Ciro Santilli has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/28449 )
Change subject: arch-arm: fix Exec trace decode of ARM atomic instructions
......................................................................
arch-arm: fix Exec trace decode of ARM atomic instructions
For example an STXR:
stxr w2, x1, [x0]
was decoding as:
stxr x1, x2, [x0]
and now it decodes as:
stxr x2, x1, [x0]
The w vs x part is still wrong and is not fixed by this patch.
MemoryEx64 seems to be the base class of all atomic instructions,
and I've verified that e.g. LDADD was also wrong and is now fixed.
Change-Id: Ic3bcb6a1d9b18f33dde5db369ac3903b443e53ae
JIRA: https://gem5.atlassian.net/browse/GEM5-484
---
M src/arch/arm/insts/mem64.cc
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/arch/arm/insts/mem64.cc b/src/arch/arm/insts/mem64.cc
index 0ddda95..9d4c391 100644
--- a/src/arch/arm/insts/mem64.cc
+++ b/src/arch/arm/insts/mem64.cc
@@ -182,9 +182,9 @@
{
std::stringstream ss;
printMnemonic(ss, "", false);
- printIntReg(ss, dest);
- ccprintf(ss, ", ");
printIntReg(ss, result);
+ ccprintf(ss, ", ");
+ printIntReg(ss, dest);
ccprintf(ss, ", [");
printIntReg(ss, base);
ccprintf(ss, "]");
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic3bcb6a1d9b18f33dde5db369ac3903b443e53ae
Gerrit-Change-Number: 28449
Gerrit-PatchSet: 1
Gerrit-Owner: Ciro Santilli <ciro.santi...@arm.com>
Gerrit-MessageType: newchange
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