Gabe Black has uploaded this change for review. ( https://gem5-review.googlesource.com/c/public/gem5/+/45523 )

Change subject: arch-riscv: Choose specialized versions of CSR ops at decode time.
......................................................................

arch-riscv: Choose specialized versions of CSR ops at decode time.

Generate specialized versions of the CSR ops which handle some special
cases, like CSRs with privilege checks and one which is made up of
several sub-registers.

Change-Id: I49c49b1ebe63dbae7ac1fb42cd194f4439c51032
---
M src/arch/riscv/isa/formats/standard.isa
1 file changed, 88 insertions(+), 79 deletions(-)



diff --git a/src/arch/riscv/isa/formats/standard.isa b/src/arch/riscv/isa/formats/standard.isa
index dba460f..23a02ff 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -287,37 +287,9 @@
         %(op_decl)s;
         %(op_rd)s;

-        switch (csr) {
-          case CSR_SATP: {
-            auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV);
-            STATUS status = xc->readMiscReg(MISCREG_STATUS);
-            if (pm == PRV_U || (pm == PRV_S && status.tvm == 1)) {
-                return std::make_shared<IllegalInstFault>(
-                        "SATP access in user mode or with TVM enabled\n",
-                        machInst);
-            }
-            break;
-          }
-          case CSR_MSTATUS: {
-            auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV);
-            if (pm != PrivilegeMode::PRV_M) {
-                return std::make_shared<IllegalInstFault>(
-                        "MSTATUS is only accessibly in machine mode\n",
-                        machInst);
-            }
-            break;
-          }
-          default:
-            break;
-        }
+        %(p_check)s;

-        RegVal data;
-        if (csr == CSR_FCSR) {
-            data = xc->readMiscReg(MISCREG_FFLAGS) |
-                   (xc->readMiscReg(MISCREG_FRM) << FRM_OFFSET);
-        } else {
-            data = xc->readMiscReg(midx);
-        }
+        RegVal data = %(r_code)s;

         DPRINTF(RiscvMisc, "Reading CSR %s: %#x\n", csrName, data);

@@ -345,38 +317,9 @@
         %(op_decl)s;
         %(op_rd)s;

-        switch (csr) {
-          case CSR_SATP: {
-            auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV);
-            STATUS status = xc->readMiscReg(MISCREG_STATUS);
-            if (pm == PRV_U || (pm == PRV_S && status.tvm == 1)) {
-                return std::make_shared<IllegalInstFault>(
-                        "SATP access in user mode or with TVM enabled\n",
-                        machInst);
-            }
-            break;
-          }
-          case CSR_MSTATUS: {
-            auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV);
-            if (pm != PrivilegeMode::PRV_M) {
-                return std::make_shared<IllegalInstFault>(
-                        "MSTATUS is only accessibly in machine mode\n",
-                        machInst);
-            }
-            break;
-          }
-          default:
-            break;
-        }
+        %(p_check)s;

-        RegVal data;
-        if (csr == CSR_FCSR) {
-            data = xc->readMiscReg(MISCREG_FFLAGS) |
-                      (xc->readMiscReg(MISCREG_FRM) << FRM_OFFSET);
-        } else {
-            data = xc->readMiscReg(midx);
-        }
-
+        RegVal data = %(r_code)s;
         RegVal original = data;

DPRINTF(RiscvMisc, "Reading CSR %s: %#x\n", csrName, data & maskVal);
@@ -389,12 +332,7 @@

         DPRINTF(RiscvMisc, "Writing %#x to CSR %s.\n", data, csrName);

-        if (csr == CSR_FCSR) {
-            xc->setMiscReg(MISCREG_FFLAGS, bits(data, 4, 0));
-            xc->setMiscReg(MISCREG_FRM, bits(data, 7, 5));
-        } else {
-            xc->setMiscReg(midx, data);
-        }
+        %(w_code)s;

         %(op_wb)s;
         return NoFault;
@@ -500,22 +438,93 @@
 }};

 def template CSRDecode {{
-    if (RS1)
-        return new %(class_name)sRw(machInst);
-    else
-        return new %(class_name)sRo(machInst);
+    if (RS1) {
+        switch (FUNCT12) {
+          case CSR_SATP:
+            return new %(class_name)sSatpRw(machInst);
+          case CSR_MSTATUS:
+            return new %(class_name)sMstatusRw(machInst);
+          case CSR_FCSR:
+            return new %(class_name)sFcsrRw(machInst);
+          default:
+            return new %(class_name)sRw(machInst);
+        }
+    } else {
+        switch (FUNCT12) {
+          case CSR_SATP:
+            return new %(class_name)sSatpRo(machInst);
+          case CSR_MSTATUS:
+            return new %(class_name)sMstatusRo(machInst);
+          case CSR_FCSR:
+            return new %(class_name)sFcsrRo(machInst);
+          default:
+            return new %(class_name)sRo(machInst);
+        }
+    }
 }};

 def format CSROp(code, *opt_flags) {{
-    iop = InstObjParams(name, Name + "Ro", 'CSROp', code, opt_flags)
-    header_output = BasicDeclare.subst(iop)
-    decoder_output = BasicConstructor.subst(iop)
-    exec_output = CSRExecuteRo.subst(iop)
+    basic_read = "xc->readMiscReg(midx);"
+    basic_write = "xc->setMiscReg(midx, data);"

-    iop = InstObjParams(name, Name + "Rw", 'CSROp', code, opt_flags)
-    header_output += BasicDeclare.subst(iop)
-    decoder_output += BasicConstructor.subst(iop)
-    exec_output += CSRExecuteRw.subst(iop)
+    satp_priv = """
+        auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV);
+        STATUS status = xc->readMiscReg(MISCREG_STATUS);
+        if (pm == PRV_U || (pm == PRV_S && status.tvm == 1)) {
+            return std::make_shared<IllegalInstFault>(
+                    "SATP access in user mode or with TVM enabled\\n",
+                    machInst);
+        }
+    """
+
+    mstatus_priv = """
+        auto pm = (PrivilegeMode)xc->readMiscReg(MISCREG_PRV);
+        if (pm != PrivilegeMode::PRV_M) {
+            return std::make_shared<IllegalInstFault>(
+                    "MSTATUS is only accessibly in machine mode\\n",
+                    machInst);
+        }
+    """
+
+    fcsr_read = """
+        xc->readMiscReg(MISCREG_FFLAGS) |
+                (xc->readMiscReg(MISCREG_FRM) << FRM_OFFSET);
+    """
+    fcsr_write = """
+            xc->setMiscReg(MISCREG_FFLAGS, bits(data, 4, 0));
+            xc->setMiscReg(MISCREG_FRM, bits(data, 7, 5));
+    """
+
+    regs = (
+        ( "", "", basic_read, basic_write ),
+        ( "Satp", satp_priv, basic_read, basic_write ),
+        ( "Mstatus", mstatus_priv, basic_read, basic_write),
+        ( "Fcsr", "", fcsr_read, fcsr_write ),
+    )
+
+    header_output = ""
+    decoder_output = ""
+    exec_output = ""
+
+    for r_name, p_check, r_code, w_code in regs:
+        snippets = {
+            "code" : code,
+            "r_name" : r_name,
+            "p_check" : p_check,
+            "r_code" : r_code,
+            "w_code" : w_code,
+        }
+        iop = InstObjParams(name, Name + r_name + "Ro", 'CSROp', snippets,
+                opt_flags)
+        header_output += BasicDeclare.subst(iop)
+        decoder_output += BasicConstructor.subst(iop)
+        exec_output += CSRExecuteRo.subst(iop)
+
+        iop = InstObjParams(name, Name + r_name + "Rw", 'CSROp', snippets,
+                opt_flags)
+        header_output += BasicDeclare.subst(iop)
+        decoder_output += BasicConstructor.subst(iop)
+        exec_output += CSRExecuteRw.subst(iop)

     iop = InstObjParams(name, Name, 'CSROp', "", opt_flags)
     decode_block = CSRDecode.subst(iop)

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/45523
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I49c49b1ebe63dbae7ac1fb42cd194f4439c51032
Gerrit-Change-Number: 45523
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-MessageType: newchange
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