Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/45525 )
Change subject: arch-riscv: Use operands instead of (read|set)MiscReg in
decoder.isa.
......................................................................
arch-riscv: Use operands instead of (read|set)MiscReg in decoder.isa.
Don't go behind the parser's back when accessing MiscReg operands.
Change-Id: Ie4f1dc34afcb7cede7f3d6ed156f1e5e6207d942
---
M src/arch/riscv/isa/decoder.isa
M src/arch/riscv/isa/operands.isa
2 files changed, 30 insertions(+), 33 deletions(-)
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 823698c..6482dd6 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -51,7 +51,7 @@
0x1: c_fld({{
offset = CIMM3 << 3 | CIMM2 << 6;
}}, {{
- STATUS status = xc->readMiscReg(MISCREG_STATUS);
+ STATUS status = Status;
if (status.fs == FPUStatus::OFF)
return std::make_shared<IllegalInstFault>("FPU is off",
machInst);
@@ -81,7 +81,7 @@
0x5: c_fsd({{
offset = CIMM3 << 3 | CIMM2 << 6;
}}, {{
- STATUS status = xc->readMiscReg(MISCREG_STATUS);
+ STATUS status = Status;
if (status.fs == FPUStatus::OFF)
return std::make_shared<IllegalInstFault>("FPU is off",
machInst);
@@ -401,7 +401,7 @@
0x01: decode FUNCT3 {
format Load {
0x2: flw({{
- STATUS status = xc->readMiscReg(MISCREG_STATUS);
+ STATUS status = Status;
if (status.fs == FPUStatus::OFF)
return std::make_shared<IllegalInstFault>(
"FPU is off", machInst);
@@ -410,7 +410,7 @@
Fd_bits = fd.v;
}}, inst_flags=FloatMemReadOp);
0x3: fld({{
- STATUS status = xc->readMiscReg(MISCREG_STATUS);
+ STATUS status = Status;
if (status.fs == FPUStatus::OFF)
return std::make_shared<IllegalInstFault>(
"FPU is off", machInst);
@@ -507,7 +507,7 @@
0x09: decode FUNCT3 {
format Store {
0x2: fsw({{
- STATUS status = xc->readMiscReg(MISCREG_STATUS);
+ STATUS status = Status;
if (status.fs == FPUStatus::OFF)
return std::make_shared<IllegalInstFault>(
"FPU is off", machInst);
@@ -515,7 +515,7 @@
Mem_uw = (uint32_t)Fs2_bits;
}}, inst_flags=FloatMemWriteOp);
0x3: fsd({{
- STATUS status = xc->readMiscReg(MISCREG_STATUS);
+ STATUS status = Status;
if (status.fs == FPUStatus::OFF)
return std::make_shared<IllegalInstFault>(
"FPU is off", machInst);
@@ -1354,7 +1354,7 @@
0x0: decode RS2 {
0x0: ecall({{
return std::make_shared<SyscallFault>(
-
(PrivilegeMode)xc->readMiscReg(MISCREG_PRV));
+ (PrivilegeMode)Prv);
}}, IsSerializeAfter, IsNonSpeculative, IsSyscall,
No_OpClass);
0x1: ebreak({{
@@ -1362,39 +1362,34 @@
xc->pcState());
}}, IsSerializeAfter, IsNonSpeculative,
No_OpClass);
0x2: uret({{
- STATUS status =
xc->readMiscReg(MISCREG_STATUS);
+ STATUS status = Status;
status.uie = status.upie;
status.upie = 1;
- xc->setMiscReg(MISCREG_STATUS, status);
- NPC = xc->readMiscReg(MISCREG_UEPC);
+ Status = status;
+ NPC = Uepc;
}}, IsSerializeAfter, IsNonSpeculative, IsReturn);
}
0x8: decode RS2 {
0x2: sret({{
- STATUS status =
xc->readMiscReg(MISCREG_STATUS);
- auto pm = (PrivilegeMode)xc->readMiscReg(
- MISCREG_PRV);
- if (pm == PRV_U ||
- (pm == PRV_S && status.tsr == 1)) {
+ STATUS status = Status;
+ if (Prv == PRV_U ||
+ (Prv == PRV_S && status.tsr == 1)) {
return std::make_shared<IllegalInstFault>(
"sret in user mode or TSR
enabled",
machInst);
- NPC = NPC;
} else {
- xc->setMiscReg(MISCREG_PRV, status.spp);
+ Prv = status.spp;
status.sie = status.spie;
status.spie = 1;
status.spp = PRV_U;
- xc->setMiscReg(MISCREG_STATUS, status);
- NPC = xc->readMiscReg(MISCREG_SEPC);
+ Status = status;
+ NPC = Sepc;
}
}}, IsSerializeAfter, IsNonSpeculative, IsReturn);
0x5: wfi({{
- STATUS status =
xc->readMiscReg(MISCREG_STATUS);
- auto pm = (PrivilegeMode)xc->readMiscReg(
- MISCREG_PRV);
- if (pm == PRV_U ||
- (pm == PRV_S && status.tw == 1)) {
+ STATUS status = Status;
+ if (Prv == PRV_U ||
+ (Prv == PRV_S && status.tw == 1)) {
return std::make_shared<IllegalInstFault>(
"wfi in user mode or TW
enabled",
machInst);
@@ -1403,9 +1398,9 @@
}}, No_OpClass);
}
0x9: sfence_vma({{
- STATUS status = xc->readMiscReg(MISCREG_STATUS);
- auto pm =
(PrivilegeMode)xc->readMiscReg(MISCREG_PRV);
- if (pm == PRV_U || (pm == PRV_S && status.tvm ==
1)) {
+ STATUS status = Status;
+ if (Prv == PRV_U ||
+ (Prv == PRV_S && status.tvm == 1)) {
return std::make_shared<IllegalInstFault>(
"sfence in user mode or TVM
enabled",
machInst);
@@ -1413,18 +1408,17 @@
xc->tcBase()->getMMUPtr()->demapPage(Rs1, Rs2);
}}, IsNonSpeculative, IsSerializeAfter, No_OpClass);
0x18: mret({{
- if (xc->readMiscReg(MISCREG_PRV) != PRV_M) {
+ if (Prv != PRV_M) {
return std::make_shared<IllegalInstFault>(
"mret at lower privilege",
machInst);
- NPC = NPC;
} else {
- STATUS status =
xc->readMiscReg(MISCREG_STATUS);
- xc->setMiscReg(MISCREG_PRV, status.mpp);
+ STATUS status = Status;
+ Prv = status.mpp;
status.mie = status.mpie;
status.mpie = 1;
status.mpp = PRV_U;
- xc->setMiscReg(MISCREG_STATUS, status);
- NPC = xc->readMiscReg(MISCREG_MEPC);
+ Status = status;
+ NPC = Mepc;
}
}}, IsSerializeAfter, IsNonSpeculative, IsReturn);
}
diff --git a/src/arch/riscv/isa/operands.isa
b/src/arch/riscv/isa/operands.isa
index 959987d..917ee06 100644
--- a/src/arch/riscv/isa/operands.isa
+++ b/src/arch/riscv/isa/operands.isa
@@ -82,6 +82,9 @@
'Frm': ('ControlReg', 'ud', 'MISCREG_FRM', None, 11),
'Prv': ('ControlReg', 'ud', 'MISCREG_PRV', None, 12),
'Status': ('ControlReg', 'status', 'MISCREG_STATUS', None, 13),
+ 'Uepc': ('ControlReg', 'ud', 'MISCREG_UEPC', None, 14),
+ 'Sepc': ('ControlReg', 'ud', 'MISCREG_SEPC', None, 15),
+ 'Mepc': ('ControlReg', 'ud', 'MISCREG_MEPC', None, 16),
#Program Counter Operands
'PC': ('PCState', 'ud', 'pc', (None, None, 'IsControl'), 7),
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ie4f1dc34afcb7cede7f3d6ed156f1e5e6207d942
Gerrit-Change-Number: 45525
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-MessageType: newchange
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