Mahyar Samani has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/31857 )
Change subject: configs: Adding DRAMSim3 models to configs
......................................................................
configs: Adding DRAMSim3 models to configs
Change-Id: Ib243444b1dd0a7b643d765731a2753314e74baff
---
M configs/common/MemConfig.py
M configs/common/Options.py
M src/mem/DRAMSim3.py
M src/mem/dramsim3.cc
4 files changed, 102 insertions(+), 19 deletions(-)
diff --git a/configs/common/MemConfig.py b/configs/common/MemConfig.py
index b530145..ae04607 100644
--- a/configs/common/MemConfig.py
+++ b/configs/common/MemConfig.py
@@ -36,10 +36,73 @@
from __future__ import print_function
from __future__ import absolute_import
+import inspect
+import os
+import sys
+from textwrap import TextWrapper
import m5.objects
from common import ObjectList
from common import HMC
+# Dictionary of mapping names of real memory controller models to
+# classes.
+_mem_classes = {}
+
+def is_mem_class(cls):
+ """Determine if a class is a memory controller that can be
instantiated"""
+
+ # We can't use the normal inspect.isclass because the ParamFactory
+ # and ProxyFactory classes have a tendency to confuse it.
+ try:
+ return issubclass(cls, m5.objects.AbstractMemory) and \
+ not cls.abstract
+ except TypeError:
+ return False
+
+def get(name):
+ """Get a memory class from a user provided class name."""
+
+ try:
+ mem_class = _mem_classes[name]
+ return mem_class
+ except KeyError:
+ print("%s is not a valid memory controller." % (name,))
+ sys.exit(1)
+
+def print_mem_list():
+ """Print a list of available memory classes."""
+
+ print("Available memory classes:")
+ doc_wrapper = TextWrapper(initial_indent="\t\t",
subsequent_indent="\t\t")
+ for name, cls in _mem_classes.items():
+ print("\t%s" % name)
+
+ # Try to extract the class documentation from the class help
+ # string.
+ doc = inspect.getdoc(cls)
+ if doc:
+ for line in doc_wrapper.wrap(doc):
+ print(line)
+
+def mem_names():
+ """Return a list of valid memory names."""
+ return _mem_classes.keys()
+
+def dramsim3_size_mb(ini_file):
+ """Parsing ini file for DRAMSim3 so that the system knows mem size"""
+ assert(os.path.exists(ini_file))
+ import ConfigParser
+ config = ConfigParser.ConfigParser()
+ config.read(ini_file)
+ channel_size = config.getint("system", "channel_size")
+ num_channels = config.getint("system", "channels")
+ size_mb = channel_size * num_channels
+ return size_mb
+
+# Add all memory controllers in the object hierarchy.
+for name, cls in inspect.getmembers(m5.objects, is_mem_class):
+ _mem_classes[name] = cls
+
def create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, intlv_size,\
xor_low_bit):
"""
@@ -114,6 +177,18 @@
opt_dram_powerdown = getattr(options, "enable_dram_powerdown", None)
opt_mem_channels_intlv = getattr(options, "mem_channels_intlv", 128)
opt_xor_low_bit = getattr(options, "xor_low_bit", 0)
+ opt_dramsim3_ini = getattr(options, 'dramsim3_ini', None)
+
+ if opt_mem_type == "DRAMSim3":
+ ini_file = ''
+ if opt_dramsim3_ini:
+ ini_file = opt_dramsim3_ini
+ else:
+ ini_file = m5.objects.DRAMSim3.config_file
+ mem_size = dramsim3_size_mb(ini_file)
+ mem_size_str = str(mem_size) + "MB"
+ options.mem_size = mem_size_str
+ system.mem_ranges = [m5.objects.AddrRange(mem_size_str)]
if opt_mem_type == "HMC_2500_1x32":
HMChost = HMC.config_hmc_host_ctrl(options, system)
@@ -165,22 +240,27 @@
# array of controllers and set their parameters to match their
# address mapping in the case of a DRAM
for r in system.mem_ranges:
- for i in range(nbr_mem_ctrls):
- mem_ctrl = create_mem_ctrl(cls, r, i, nbr_mem_ctrls,
intlv_bits,
- intlv_size, opt_xor_low_bit)
- # Set the number of ranks based on the command-line
- # options if it was explicitly set
- if issubclass(cls, m5.objects.DRAMCtrl) and opt_mem_ranks:
- mem_ctrl.ranks_per_channel = opt_mem_ranks
+ for i in xrange(nbr_mem_ctrls):
+ # We need to do a couple of things differently for DRAMSim3
+ # use same outdir as gem5, and use its own address mapping
+ if opt_mem_type == 'DRAMSim3':
+ mem_ctrl = cls()
+ if opt_dramsim3_ini:
+ mem_ctrl.config_file = opt_dramsim3_ini
+ mem_ctrl.file_path = m5.options.outdir
+ mem_ctrl.range = m5.objects.AddrRange(r.size())
+ else:
+ mem_ctrl = create_mem_ctrl(cls, r, i, nbr_mem_ctrls,
+ intlv_bits, intlv_size, xor_low_bit)
+ # Set the number of ranks based on the command-line
+ # options if it was explicitly set
+ if issubclass(cls, m5.objects.DRAMCtrl) and opt_mem_ranks:
+ mem_ctrl.ranks_per_channel = opt_mem_ranks
- # Enable low-power DRAM states if option is set
- if issubclass(cls, m5.objects.DRAMCtrl):
- mem_ctrl.enable_dram_powerdown = opt_dram_powerdown
-
- if opt_elastic_trace_en:
- mem_ctrl.latency = '1ns'
- print("For elastic trace, over-riding Simple Memory "
- "latency to 1ns.")
+ if opt_elastic_trace_en:
+ mem_ctrl.latency = '1ns'
+ print("For elastic trace, over-riding Simple Memory "
+ "latency to 1ns.")
mem_ctrls.append(mem_ctrl)
diff --git a/configs/common/Options.py b/configs/common/Options.py
index 0409fb8..af49893 100644
--- a/configs/common/Options.py
+++ b/configs/common/Options.py
@@ -113,9 +113,12 @@
parser.add_option("--mem-channels-intlv", type="int", default=0,
help="Memory channels interleave")
-
parser.add_option("--memchecker", action="store_true")
+ # DRAMSim3 option
+ parser.add_option("--dramsim3-ini", type="string", default=None,
+ help = "dramsim3 config file")
+
# Cache Options
parser.add_option("--external-memory-system", type="string",
help="use external ports of this port_type for
caches")
diff --git a/src/mem/DRAMSim3.py b/src/mem/DRAMSim3.py
index d33d001..c8f3efe 100644
--- a/src/mem/DRAMSim3.py
+++ b/src/mem/DRAMSim3.py
@@ -46,8 +46,8 @@
# A single port for now
port = SlavePort("Slave port")
- configFile = Param.String("ext/dramsim3/DRAMSim3/configs/"
+ config_file = Param.String("ext/dramsim3/DRAMSim3/configs/"
"DDR4_8Gb_x8_2400.ini",
"One configuration file")
- filePath = Param.String("ext/dramsim3/DRAMSim3/",
+ file_path = Param.String("ext/dramsim3/DRAMSim3/",
"Directory to prepend to file names")
diff --git a/src/mem/dramsim3.cc b/src/mem/dramsim3.cc
index a18e1f4..6d37567 100644
--- a/src/mem/dramsim3.cc
+++ b/src/mem/dramsim3.cc
@@ -52,7 +52,7 @@
this, 0, std::placeholders::_1)),
write_cb(std::bind(&DRAMSim3::writeComplete,
this, 0, std::placeholders::_1)),
- wrapper(p->configFile, p->filePath, read_cb, write_cb),
+ wrapper(p->config_file, p->file_path, read_cb, write_cb),
retryReq(false), retryResp(false), startTick(0),
nbrOutstandingReads(0), nbrOutstandingWrites(0),
sendResponseEvent([this]{ sendResponse(); }, name()),
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib243444b1dd0a7b643d765731a2753314e74baff
Gerrit-Change-Number: 31857
Gerrit-PatchSet: 1
Gerrit-Owner: Mahyar Samani <msam...@ucdavis.edu>
Gerrit-MessageType: newchange
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