Mahyar Samani has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/40515 )
Change subject: cpu: Adding stridedGen
......................................................................
cpu: Adding stridedGen
This patch adds the source code for a mode of traffic generator to
generate strided access pattern to the memory. The main difference
between a stridedGen and linearGen are in the way startAddr and
nextAddr are set. In stridedGen instead of increasing the current
address by blocksize to generate nextAddr, it is increased by
strideSize. Also, the offset param is used to indicate the order
of any instances of traffic generator in an array (similar to
threadId.x in CUDA)
Change-Id: I80df414faf1c73f68e87400654675a553de0caa5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40515
Maintainer: Jason Lowe-Power <power...@gmail.com>
Tested-by: kokoro <noreply+kok...@google.com>
Reviewed-by: Jason Lowe-Power <power...@gmail.com>
---
M src/cpu/testers/traffic_gen/PyTrafficGen.py
M src/cpu/testers/traffic_gen/SConscript
M src/cpu/testers/traffic_gen/base.cc
M src/cpu/testers/traffic_gen/base.hh
A src/cpu/testers/traffic_gen/strided_gen.cc
A src/cpu/testers/traffic_gen/strided_gen.hh
6 files changed, 269 insertions(+), 0 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/cpu/testers/traffic_gen/PyTrafficGen.py
b/src/cpu/testers/traffic_gen/PyTrafficGen.py
index 962f8e0..baf4ef5 100644
--- a/src/cpu/testers/traffic_gen/PyTrafficGen.py
+++ b/src/cpu/testers/traffic_gen/PyTrafficGen.py
@@ -60,6 +60,7 @@
PyBindMethod("createDramRot"),
PyBindMethod("createHybrid"),
PyBindMethod("createNvm"),
+ PyBindMethod("createStrided")
]
@cxxMethod(override=True)
diff --git a/src/cpu/testers/traffic_gen/SConscript
b/src/cpu/testers/traffic_gen/SConscript
index 987ed67..640d81a 100644
--- a/src/cpu/testers/traffic_gen/SConscript
+++ b/src/cpu/testers/traffic_gen/SConscript
@@ -49,6 +49,7 @@
Source('nvm_gen.cc')
Source('random_gen.cc')
Source('stream_gen.cc')
+Source('strided_gen.cc')
DebugFlag('TrafficGen')
SimObject('BaseTrafficGen.py')
diff --git a/src/cpu/testers/traffic_gen/base.cc
b/src/cpu/testers/traffic_gen/base.cc
index 320de92..3c28d00 100644
--- a/src/cpu/testers/traffic_gen/base.cc
+++ b/src/cpu/testers/traffic_gen/base.cc
@@ -51,6 +51,7 @@
#include "cpu/testers/traffic_gen/nvm_gen.hh"
#include "cpu/testers/traffic_gen/random_gen.hh"
#include "cpu/testers/traffic_gen/stream_gen.hh"
+#include "cpu/testers/traffic_gen/strided_gen.hh"
#include "debug/Checkpoint.hh"
#include "debug/TrafficGen.hh"
#include "enums/AddrMap.hh"
@@ -520,6 +521,22 @@
}
std::shared_ptr<BaseGen>
+BaseTrafficGen::createStrided(Tick duration,
+ Addr start_addr, Addr end_addr, Addr
blocksize,
+ Addr stride_size, int gen_id,
+ Tick min_period, Tick max_period,
+ uint8_t read_percent, Addr data_limit)
+{
+ return std::shared_ptr<BaseGen>(new StridedGen(*this, requestorId,
+ duration, start_addr,
+ end_addr, blocksize,
+ system->cacheLineSize(),
+ stride_size, gen_id,
+ min_period, max_period,
+ read_percent,
data_limit));
+}
+
+std::shared_ptr<BaseGen>
BaseTrafficGen::createTrace(Tick duration,
const std::string& trace_file, Addr
addr_offset)
{
diff --git a/src/cpu/testers/traffic_gen/base.hh
b/src/cpu/testers/traffic_gen/base.hh
index 018028b..a1a1efc 100644
--- a/src/cpu/testers/traffic_gen/base.hh
+++ b/src/cpu/testers/traffic_gen/base.hh
@@ -314,6 +314,13 @@
Enums::AddrMap addr_mapping,
unsigned int nbr_of_ranks);
+ std::shared_ptr<BaseGen> createStrided(
+ Tick duration,
+ Addr start_addr, Addr end_addr, Addr blocksize,
+ Addr stride_size, int gen_id,
+ Tick min_period, Tick max_period,
+ uint8_t read_percent, Addr data_limit);
+
std::shared_ptr<BaseGen> createTrace(
Tick duration,
const std::string& trace_file, Addr addr_offset);
diff --git a/src/cpu/testers/traffic_gen/strided_gen.cc
b/src/cpu/testers/traffic_gen/strided_gen.cc
new file mode 100644
index 0000000..0b77872
--- /dev/null
+++ b/src/cpu/testers/traffic_gen/strided_gen.cc
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2012-2013, 2016-2017 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed here under. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "cpu/testers/traffic_gen/strided_gen.hh"
+
+#include <algorithm>
+
+#include "base/random.hh"
+#include "base/trace.hh"
+#include "debug/TrafficGen.hh"
+
+void
+StridedGen::enter()
+{
+ // reset the address and the data counter
+ nextAddr = startAddr + genID * blocksize;
+ dataManipulated = 0;
+}
+
+PacketPtr
+StridedGen::getNextPacket()
+{
+ // choose if we generate a read or a write here
+ bool isRead = readPercent != 0 &&
+ (readPercent == 100 || random_mt.random(0, 100) < readPercent);
+
+ assert((readPercent == 0 && !isRead) || (readPercent == 100 && isRead)
||
+ readPercent != 100);
+
+ DPRINTF(TrafficGen, "StridedGen::getNextPacket: %c to addr %x,
size %d\n",
+ isRead ? 'r' : 'w', nextAddr, blocksize);
+
+ // Add the amount of data manipulated to the total
+ dataManipulated += blocksize;
+
+ PacketPtr pkt = getPacket(nextAddr, blocksize,
+ isRead ? MemCmd::ReadReq : MemCmd::WriteReq);
+
+ // increment the address
+ nextAddr += strideSize;
+
+ // If we have reached the end of the address space, reset the
+ // address to the start of the range
+ if (nextAddr > endAddr) {
+ DPRINTF(TrafficGen, "Wrapping address to the start of "
+ "the range\n");
+ nextAddr = startAddr + genID * blocksize;
+ }
+
+ return pkt;
+}
+
+Tick
+StridedGen::nextPacketTick(bool elastic, Tick delay) const
+{
+ // Check to see if we have reached the data limit. If dataLimit is
+ // zero we do not have a data limit and therefore we will keep
+ // generating requests for the entire residency in this state.
+ if (dataLimit && dataManipulated >= dataLimit) {
+ DPRINTF(TrafficGen, "Data limit for StridedGen reached.\n");
+ // there are no more requests, therefore return MaxTick
+ return MaxTick;
+ } else {
+ // return the time when the next request should take place
+ Tick wait = random_mt.random(minPeriod, maxPeriod);
+
+ // compensate for the delay experienced to not be elastic, by
+ // default the value we generate is from the time we are
+ // asked, so the elasticity happens automatically
+ if (!elastic) {
+ if (wait < delay)
+ wait = 0;
+ else
+ wait -= delay;
+ }
+
+ return curTick() + wait;
+ }
+}
diff --git a/src/cpu/testers/traffic_gen/strided_gen.hh
b/src/cpu/testers/traffic_gen/strided_gen.hh
new file mode 100644
index 0000000..d0a1391
--- /dev/null
+++ b/src/cpu/testers/traffic_gen/strided_gen.hh
@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2012-2013, 2017-2018 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed here under. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * @file
+ * Declaration of the strided generator that generates sequential
+ * requests.
+ */
+
+#ifndef __CPU_TRAFFIC_GEN_STRIDED_GEN_HH__
+#define __CPU_TRAFFIC_GEN_STRIDED_GEN_HH__
+
+#include "base/bitfield.hh"
+#include "base/intmath.hh"
+#include "base_gen.hh"
+#include "mem/packet.hh"
+
+/**
+ * The strided generator generates sequential requests from a
+ * start to an end address, with a fixed block size. A
+ * fraction of the requests are reads, as determined by the
+ * read percent. There is an optional data limit for when to
+ * stop generating new requests.
+ */
+class StridedGen : public StochasticGen
+{
+
+ public:
+
+ /**
+ * Create a strided address sequence generator. Set
+ * min_period == max_period for a fixed inter-transaction
+ * time.
+ *
+ * @param obj SimObject owning this sequence generator
+ * @param requestor_id RequestorID related to the memory requests
+ * @param _duration duration of this state before transitioning
+ * @param start_addr Start address
+ * @param end_addr End address
+ * @param _blocksize Size used for transactions injected
+ * @param cacheline_size cache line size in the system
+ * @param stride_size The strided size for consecutive requests
+ * @param gen_id The order of traffic generator in a list of strided \
+ * traffic generators, this param is used to offset the start address
of \
+ * each generator accordingly with others.
+ * @param min_period Lower limit of random inter-transaction time
+ * @param max_period Upper limit of random inter-transaction time
+ * @param read_percent Percent of transactions that are reads
+ * @param data_limit Upper limit on how much data to read/write
+ */
+ StridedGen(SimObject &obj,
+ RequestorID requestor_id, Tick _duration,
+ Addr start_addr, Addr end_addr,
+ Addr _blocksize, Addr cacheline_size,
+ Addr stride_size, int gen_id,
+ Tick min_period, Tick max_period,
+ uint8_t read_percent, Addr data_limit)
+ : StochasticGen(obj, requestor_id, _duration, start_addr, end_addr,
+ _blocksize, cacheline_size, min_period, max_period,
+ read_percent, data_limit),
+ nextAddr(0),
+ dataManipulated(0),
+ strideSize(stride_size),
+ genID(gen_id)
+ { }
+
+ void enter();
+
+ PacketPtr getNextPacket();
+
+ Tick nextPacketTick(bool elastic, Tick delay) const;
+
+ private:
+ /** Address of next request */
+ Addr nextAddr;
+
+ /**
+ * Counter to determine the amount of data
+ * manipulated. Used to determine if we should continue
+ * generating requests.
+ */
+ Addr dataManipulated;
+
+ /* The size by which consequent requests are separated */
+ Addr strideSize;
+
+ /**
+ * This param is used to indicate the order of a traffic
+ * generator among a set of traffic generators, then it
+ * is used to calculate the start address separately for
+ * each traffic generator in a list of generators.
+ */
+ int genID;
+};
+
+#endif
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I80df414faf1c73f68e87400654675a553de0caa5
Gerrit-Change-Number: 40515
Gerrit-PatchSet: 5
Gerrit-Owner: Mahyar Samani <msam...@ucdavis.edu>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-Reviewer: Jason Lowe-Power <power...@gmail.com>
Gerrit-Reviewer: Mahyar Samani <msam...@ucdavis.edu>
Gerrit-Reviewer: Nikos Nikoleris <nikos.nikole...@arm.com>
Gerrit-Reviewer: Tiago Mück <tiago.m...@arm.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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