Hello Giacomo Travaglini,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/34976
to review the following change.
Change subject: cpu: BaseCPU using ArchMMU instead of ArchDTB/ArchITB
......................................................................
cpu: BaseCPU using ArchMMU instead of ArchDTB/ArchITB
With this commit we replace every TLB pointer stored in the
cpu model with a BaseMMU pointer.
Change-Id: I4932a32f68582b25cd252b5420b54d6a40ee15b8
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M configs/example/arm/devices.py
M configs/example/fs.py
M configs/learning_gem5/part3/msi_caches.py
M configs/learning_gem5/part3/ruby_caches_MI_example.py
M src/arch/arm/tlb.hh
M src/arch/generic/SConscript
A src/arch/generic/tlb.cc
M src/arch/generic/tlb.hh
M src/cpu/BaseCPU.py
M src/cpu/base.cc
M src/cpu/base.hh
M src/cpu/base_dyn_inst.hh
M src/cpu/checker/cpu.cc
M src/cpu/checker/cpu.hh
M src/cpu/checker/cpu_impl.hh
M src/cpu/checker/thread_context.hh
M src/cpu/kvm/base.cc
M src/cpu/minor/cpu.cc
M src/cpu/minor/exec_context.hh
M src/cpu/minor/fetch1.cc
M src/cpu/minor/lsq.cc
M src/cpu/o3/O3CPU.py
M src/cpu/o3/cpu.cc
M src/cpu/o3/cpu.hh
M src/cpu/o3/fetch_impl.hh
M src/cpu/o3/lsq_impl.hh
M src/cpu/o3/lsq_unit.hh
M src/cpu/o3/thread_context.hh
M src/cpu/simple/BaseSimpleCPU.py
M src/cpu/simple/atomic.cc
M src/cpu/simple/base.cc
M src/cpu/simple/exec_context.hh
M src/cpu/simple/timing.cc
M src/cpu/simple_thread.cc
M src/cpu/simple_thread.hh
M src/cpu/thread_context.hh
M tests/configs/pc-simple-timing-ruby.py
M tests/gem5/x86-boot-tests/system/caches.py
38 files changed, 250 insertions(+), 151 deletions(-)
diff --git a/configs/example/arm/devices.py b/configs/example/arm/devices.py
index cc8ac5e..eb2421b 100644
--- a/configs/example/arm/devices.py
+++ b/configs/example/arm/devices.py
@@ -179,7 +179,8 @@
int_cls = ArmPPI if pint < 32 else ArmSPI
for isa in cpu.isa:
isa.pmu = ArmPMU(interrupt=int_cls(num=pint))
- isa.pmu.addArchEvents(cpu=cpu, itb=cpu.itb, dtb=cpu.dtb,
+ isa.pmu.addArchEvents(cpu=cpu,
+ itb=cpu.mmu.itb, dtb=cpu.mmu.dtb,
icache=getattr(cpu, 'icache', None),
dcache=getattr(cpu, 'dcache', None),
l2cache=getattr(self, 'l2', None))
diff --git a/configs/example/fs.py b/configs/example/fs.py
index d39feee..ab1f134 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -176,8 +176,8 @@
cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
if buildEnv['TARGET_ISA'] in ("x86", "arm"):
- cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
- cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
+ cpu.mmu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
+ cpu.mmu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
if buildEnv['TARGET_ISA'] in "x86":
cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master
diff --git a/configs/learning_gem5/part3/msi_caches.py
b/configs/learning_gem5/part3/msi_caches.py
index f899426..5066996 100644
--- a/configs/learning_gem5/part3/msi_caches.py
+++ b/configs/learning_gem5/part3/msi_caches.py
@@ -114,8 +114,8 @@
cpu.interrupts[0].int_master = self.sequencers[i].slave
cpu.interrupts[0].int_slave = self.sequencers[i].master
if isa == 'x86' or isa == 'arm':
- cpu.itb.walker.port = self.sequencers[i].slave
- cpu.dtb.walker.port = self.sequencers[i].slave
+ cpu.mmu.itb.walker.port = self.sequencers[i].slave
+ cpu.mmu.dtb.walker.port = self.sequencers[i].slave
class L1Cache(L1Cache_Controller):
diff --git a/configs/learning_gem5/part3/ruby_caches_MI_example.py
b/configs/learning_gem5/part3/ruby_caches_MI_example.py
index 29b66a6..685f66a 100644
--- a/configs/learning_gem5/part3/ruby_caches_MI_example.py
+++ b/configs/learning_gem5/part3/ruby_caches_MI_example.py
@@ -112,8 +112,8 @@
cpu.interrupts[0].int_master = self.sequencers[i].slave
cpu.interrupts[0].int_slave = self.sequencers[i].master
if isa == 'x86' or isa == 'arm':
- cpu.itb.walker.port = self.sequencers[i].slave
- cpu.dtb.walker.port = self.sequencers[i].slave
+ cpu.mmu.itb.walker.port = self.sequencers[i].slave
+ cpu.mmu.dtb.walker.port = self.sequencers[i].slave
class L1Cache(L1Cache_Controller):
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index ac9c383..dfe09ce 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -51,6 +51,7 @@
#include "mem/request.hh"
#include "params/ArmMMU.hh"
#include "params/ArmTLB.hh"
+#include "params/ArmMMU.hh"
#include "sim/probe/pmu.hh"
class ThreadContext;
diff --git a/src/arch/generic/SConscript b/src/arch/generic/SConscript
index 22654cd..a41ee59 100644
--- a/src/arch/generic/SConscript
+++ b/src/arch/generic/SConscript
@@ -45,6 +45,8 @@
Source('decode_cache.cc')
Source('decoder.cc')
+Source('pseudo_inst.cc')
+Source('tlb.cc')
SimObject('BaseInterrupts.py')
SimObject('BaseISA.py')
@@ -52,4 +54,3 @@
SimObject('ISACommon.py')
DebugFlag('TLB')
-Source('pseudo_inst.cc')
diff --git a/src/arch/generic/tlb.cc b/src/arch/generic/tlb.cc
new file mode 100644
index 0000000..bbd8ce6
--- /dev/null
+++ b/src/arch/generic/tlb.cc
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2011-2012,2016-2017, 2019-2020 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * Copyright (c) 2011 Regents of the University of California
+ * Copyright (c) 2013 Advanced Micro Devices, Inc.
+ * Copyright (c) 2013 Mark D. Hill and David A. Wood
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "arch/generic/tlb.hh"
+
+void
+BaseMMU::takeOverFrom(BaseMMU *old_mmu)
+{
+ Port *old_itb_port = old_mmu->itb->getTableWalkerPort();
+ Port *old_dtb_port = old_mmu->dtb->getTableWalkerPort();
+ Port *new_itb_port = itb->getTableWalkerPort();
+ Port *new_dtb_port = dtb->getTableWalkerPort();
+
+ // Move over any table walker ports if they exist
+ if (new_itb_port)
+ new_itb_port->takeOverFrom(old_itb_port);
+ if (new_dtb_port)
+ new_dtb_port->takeOverFrom(old_dtb_port);
+
+ itb->takeOverFrom(old_mmu->itb);
+ dtb->takeOverFrom(old_mmu->dtb);
+}
diff --git a/src/arch/generic/tlb.hh b/src/arch/generic/tlb.hh
index 59e9f3b..8b5a1cb 100644
--- a/src/arch/generic/tlb.hh
+++ b/src/arch/generic/tlb.hh
@@ -171,6 +171,47 @@
dtb->demapPage(vaddr, asn);
}
+ Fault
+ translateAtomic(const RequestPtr &req, ThreadContext *tc,
BaseTLB::Mode mode)
+ {
+ if (mode == BaseTLB::Execute)
+ return itb->translateAtomic(req, tc, mode);
+ else
+ return dtb->translateAtomic(req, tc, mode);
+ }
+
+ void
+ translateTiming(const RequestPtr &req, ThreadContext *tc,
+ BaseTLB::Translation *translation, BaseTLB::Mode mode)
+ {
+ if (mode == BaseTLB::Execute)
+ return itb->translateTiming(req, tc, translation, mode);
+ else
+ return dtb->translateTiming(req, tc, translation, mode);
+ }
+
+ Fault
+ translateFunctional(const RequestPtr &req, ThreadContext *tc,
+ BaseTLB::Mode mode)
+ {
+ if (mode == BaseTLB::Execute)
+ return itb->translateFunctional(req, tc, mode);
+ else
+ return dtb->translateFunctional(req, tc, mode);
+ }
+
+ Fault
+ finalizePhysical(const RequestPtr &req, ThreadContext *tc,
+ BaseTLB::Mode mode) const
+ {
+ if (mode == BaseTLB::Execute)
+ return itb->finalizePhysical(req, tc, mode);
+ else
+ return dtb->finalizePhysical(req, tc, mode);
+ }
+
+ void takeOverFrom(BaseMMU *old_mmu);
+
public:
BaseTLB* dtb;
BaseTLB* itb;
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index ad91f3a..8f0a325 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -59,27 +59,27 @@
default_tracer = ExeTracer()
if buildEnv['TARGET_ISA'] == 'sparc':
- from m5.objects.SparcTLB import SparcTLB as ArchDTB, SparcTLB as
ArchITB
+ from m5.objects.SparcTLB import SparcMMU as ArchMMU
from m5.objects.SparcInterrupts import SparcInterrupts as
ArchInterrupts
from m5.objects.SparcISA import SparcISA as ArchISA
elif buildEnv['TARGET_ISA'] == 'x86':
- from m5.objects.X86TLB import X86TLB as ArchDTB, X86TLB as ArchITB
+ from m5.objects.X86TLB import X86MMU as ArchMMU
from m5.objects.X86LocalApic import X86LocalApic as ArchInterrupts
from m5.objects.X86ISA import X86ISA as ArchISA
elif buildEnv['TARGET_ISA'] == 'mips':
- from m5.objects.MipsTLB import MipsTLB as ArchDTB, MipsTLB as ArchITB
+ from m5.objects.MipsTLB import MipsMMU as ArchMMU
from m5.objects.MipsInterrupts import MipsInterrupts as ArchInterrupts
from m5.objects.MipsISA import MipsISA as ArchISA
elif buildEnv['TARGET_ISA'] == 'arm':
- from m5.objects.ArmTLB import ArmDTB as ArchDTB, ArmITB as ArchITB
+ from m5.objects.ArmTLB import ArmMMU as ArchMMU
from m5.objects.ArmInterrupts import ArmInterrupts as ArchInterrupts
from m5.objects.ArmISA import ArmISA as ArchISA
elif buildEnv['TARGET_ISA'] == 'power':
- from m5.objects.PowerTLB import PowerTLB as ArchDTB, PowerTLB as
ArchITB
+ from m5.objects.PowerTLB import PowerMMU as ArchMMU
from m5.objects.PowerInterrupts import PowerInterrupts as
ArchInterrupts
from m5.objects.PowerISA import PowerISA as ArchISA
elif buildEnv['TARGET_ISA'] == 'riscv':
- from m5.objects.RiscvTLB import RiscvTLB as ArchDTB, RiscvTLB as
ArchITB
+ from m5.objects.RiscvTLB import RiscvMMU as ArchMMU
from m5.objects.RiscvInterrupts import RiscvInterrupts as
ArchInterrupts
from m5.objects.RiscvISA import RiscvISA as ArchISA
else:
@@ -153,8 +153,7 @@
workload = VectorParam.Process([], "processes to run")
- dtb = Param.BaseTLB(ArchDTB(), "Data TLB")
- itb = Param.BaseTLB(ArchITB(), "Instruction TLB")
+ mmu = Param.BaseMMU(ArchMMU(), "CPU memory management unit")
if buildEnv['TARGET_ISA'] == 'power':
UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
interrupts = VectorParam.BaseInterrupts([], "Interrupt Controller")
@@ -180,7 +179,7 @@
_cached_ports = ['icache_port', 'dcache_port']
if buildEnv['TARGET_ISA'] in ['x86', 'arm', 'riscv']:
- _cached_ports += ["itb.walker.port", "dtb.walker.port"]
+ _cached_ports += ["mmu.itb.walker.port", "mmu.dtb.walker.port"]
_uncached_interrupt_response_ports = []
_uncached_interrupt_request_ports = []
@@ -218,12 +217,13 @@
if iwc and dwc:
self.itb_walker_cache = iwc
self.dtb_walker_cache = dwc
- self.itb.walker.port = iwc.cpu_side
- self.dtb.walker.port = dwc.cpu_side
+ self.mmu.itb.walker.port = iwc.cpu_side
+ self.mmu.dtb.walker.port = dwc.cpu_side
self._cached_ports += ["itb_walker_cache.mem_side", \
"dtb_walker_cache.mem_side"]
else:
- self._cached_ports +=
["itb.walker.port", "dtb.walker.port"]
+ self._cached_ports += ["mmu.itb.walker.port",
+ "mmu.dtb.walker.port"]
# Checker doesn't need its own tlb caches because it does
# functional accesses only
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index ef843d7..13db0fc 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -235,7 +235,7 @@
}
void
-BaseCPU::mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseTLB *dtb)
+BaseCPU::mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseMMU *mmu)
{
assert(tid < numThreads);
AddressMonitor &monitor = addressMonitor[tid];
@@ -256,7 +256,7 @@
req->setVirt(addr, size, 0x0, dataRequestorId(), tc->instAddr());
// translate to physical address
- Fault fault = dtb->translateAtomic(req, tc, BaseTLB::Read);
+ Fault fault = mmu->translateAtomic(req, tc, BaseTLB::Read);
assert(fault == NoFault);
monitor.pAddr = req->getPaddr() & mask;
@@ -588,41 +588,14 @@
ThreadContext::compare(oldTC, newTC);
*/
- Port *old_itb_port = oldTC->getITBPtr()->getTableWalkerPort();
- Port *old_dtb_port = oldTC->getDTBPtr()->getTableWalkerPort();
- Port *new_itb_port = newTC->getITBPtr()->getTableWalkerPort();
- Port *new_dtb_port = newTC->getDTBPtr()->getTableWalkerPort();
-
- // Move over any table walker ports if they exist
- if (new_itb_port)
- new_itb_port->takeOverFrom(old_itb_port);
- if (new_dtb_port)
- new_dtb_port->takeOverFrom(old_dtb_port);
- newTC->getITBPtr()->takeOverFrom(oldTC->getITBPtr());
- newTC->getDTBPtr()->takeOverFrom(oldTC->getDTBPtr());
+ newTC->getMMUPtr()->takeOverFrom(oldTC->getMMUPtr());
// Checker whether or not we have to transfer CheckerCPU
// objects over in the switch
- CheckerCPU *oldChecker = oldTC->getCheckerCpuPtr();
- CheckerCPU *newChecker = newTC->getCheckerCpuPtr();
- if (oldChecker && newChecker) {
- Port *old_checker_itb_port =
- oldChecker->getITBPtr()->getTableWalkerPort();
- Port *old_checker_dtb_port =
- oldChecker->getDTBPtr()->getTableWalkerPort();
- Port *new_checker_itb_port =
- newChecker->getITBPtr()->getTableWalkerPort();
- Port *new_checker_dtb_port =
- newChecker->getDTBPtr()->getTableWalkerPort();
-
- newChecker->getITBPtr()->takeOverFrom(oldChecker->getITBPtr());
- newChecker->getDTBPtr()->takeOverFrom(oldChecker->getDTBPtr());
-
- // Move over any table walker ports if they exist for checker
- if (new_checker_itb_port)
- new_checker_itb_port->takeOverFrom(old_checker_itb_port);
- if (new_checker_dtb_port)
- new_checker_dtb_port->takeOverFrom(old_checker_dtb_port);
+ CheckerCPU *old_checker = oldTC->getCheckerCpuPtr();
+ CheckerCPU *new_checker = newTC->getCheckerCpuPtr();
+ if (old_checker && new_checker) {
+
new_checker->getMMUPtr()->takeOverFrom(old_checker->getMMUPtr());
}
}
@@ -647,11 +620,9 @@
ThreadContext &tc(*threadContexts[i]);
CheckerCPU *checker(tc.getCheckerCpuPtr());
- tc.getITBPtr()->flushAll();
- tc.getDTBPtr()->flushAll();
+ tc.getMMUPtr()->flushAll();
if (checker) {
- checker->getITBPtr()->flushAll();
- checker->getDTBPtr()->flushAll();
+ checker->getMMUPtr()->flushAll();
}
}
}
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 9cf4baa..f67ac26 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -612,7 +612,7 @@
public:
void armMonitor(ThreadID tid, Addr address);
bool mwait(ThreadID tid, PacketPtr pkt);
- void mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseTLB *dtb);
+ void mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseMMU *mmu);
AddressMonitor *getCpuAddrMonitor(ThreadID tid)
{
assert(tid < numThreads);
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index fd216b1..024977f 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -1054,7 +1054,7 @@
void
mwaitAtomic(ThreadContext *tc) override
{
- return cpu->mwaitAtomic(threadNumber, tc, cpu->dtb);
+ return cpu->mwaitAtomic(threadNumber, tc, cpu->mmu);
}
AddressMonitor *
getAddrMonitor() override
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index fe0300e..1157f99 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -80,8 +80,7 @@
exitOnError = p->exitOnError;
warnOnlyOnLoadError = p->warnOnlyOnLoadError;
- itb = p->itb;
- dtb = p->dtb;
+ mmu = p->mmu;
workload = p->workload;
updateOnError = true;
@@ -99,11 +98,11 @@
systemPtr = system;
if (FullSystem) {
- thread = new SimpleThread(this, 0, systemPtr, itb, dtb, p->isa[0]);
+ thread = new SimpleThread(this, 0, systemPtr, mmu, p->isa[0]);
} else {
thread = new SimpleThread(this, 0, systemPtr,
workload.size() ? workload[0] : NULL,
- itb, dtb, p->isa[0]);
+ mmu, p->isa[0]);
}
tc = thread->getTC();
@@ -194,7 +193,7 @@
// translate to physical address
if (predicate) {
- fault = dtb->translateFunctional(mem_req, tc, BaseTLB::Read);
+ fault = mmu->translateFunctional(mem_req, tc, BaseTLB::Read);
}
if (predicate && !checked_flags && fault == NoFault &&
unverifiedReq) {
@@ -278,7 +277,7 @@
predicate = (mem_req != nullptr);
if (predicate) {
- fault = dtb->translateFunctional(mem_req, tc, BaseTLB::Write);
+ fault = mmu->translateFunctional(mem_req, tc, BaseTLB::Write);
}
if (predicate && !checked_flags && fault == NoFault &&
unverifiedReq) {
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index f5d7834..a1c5e54 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -132,8 +132,7 @@
ThreadContext *tc;
- BaseTLB *itb;
- BaseTLB *dtb;
+ BaseMMU *mmu;
// ISAs like ARM can have multiple destination registers to check,
// keep them all in a std::queue
@@ -153,8 +152,10 @@
// Primary thread being run.
SimpleThread *thread;
- BaseTLB* getITBPtr() { return itb; }
- BaseTLB* getDTBPtr() { return dtb; }
+ BaseTLB* getITBPtr() { return mmu->itb; }
+ BaseTLB* getDTBPtr() { return mmu->dtb; }
+
+ BaseMMU* getMMUPtr() { return mmu; }
virtual Counter totalInsts() const override
{
@@ -540,28 +541,32 @@
void
demapPage(Addr vaddr, uint64_t asn) override
{
- this->itb->demapPage(vaddr, asn);
- this->dtb->demapPage(vaddr, asn);
+ mmu->demapPage(vaddr, asn);
}
// monitor/mwait funtions
void armMonitor(Addr address) override { BaseCPU::armMonitor(0,
address); }
bool mwait(PacketPtr pkt) override { return BaseCPU::mwait(0, pkt); }
- void mwaitAtomic(ThreadContext *tc) override
- { return BaseCPU::mwaitAtomic(0, tc, thread->dtb); }
+
+ void
+ mwaitAtomic(ThreadContext *tc) override
+ {
+ return BaseCPU::mwaitAtomic(0, tc, thread->mmu);
+ }
+
AddressMonitor *getAddrMonitor() override
{ return BaseCPU::getCpuAddrMonitor(0); }
void
demapInstPage(Addr vaddr, uint64_t asn)
{
- this->itb->demapPage(vaddr, asn);
+ mmu->itb->demapPage(vaddr, asn);
}
void
demapDataPage(Addr vaddr, uint64_t asn)
{
- this->dtb->demapPage(vaddr, asn);
+ mmu->dtb->demapPage(vaddr, asn);
}
/**
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 4fab375..a4a6323 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -244,7 +244,7 @@
Request::INST_FETCH, requestorId,
thread->instAddr());
- fault = itb->translateFunctional(
+ fault = mmu->translateFunctional(
mem_req, tc, BaseTLB::Execute);
if (fault != NoFault) {
diff --git a/src/cpu/checker/thread_context.hh
b/src/cpu/checker/thread_context.hh
index d07de62..5a68be4 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -131,6 +131,8 @@
BaseTLB *getDTBPtr() override { return actualTC->getDTBPtr(); }
+ BaseMMU *getMMUPtr() override { return actualTC->getMMUPtr(); }
+
CheckerCPU *
getCheckerCpuPtr() override
{
diff --git a/src/cpu/kvm/base.cc b/src/cpu/kvm/base.cc
index 83992cd..b98523c 100644
--- a/src/cpu/kvm/base.cc
+++ b/src/cpu/kvm/base.cc
@@ -83,12 +83,12 @@
errno);
if (FullSystem)
- thread = new SimpleThread(this, 0, params->system, params->itb,
params->dtb,
+ thread = new SimpleThread(this, 0, params->system, params->mmu,
params->isa[0]);
else
thread = new SimpleThread(this, /* thread_num */ 0, params->system,
- params->workload[0], params->itb,
- params->dtb, params->isa[0]);
+ params->workload[0], params->mmu,
+ params->isa[0]);
thread->setStatus(ThreadContext::Halted);
tc = thread->getTC();
@@ -1081,7 +1081,7 @@
// APIC accesses on x86 and m5ops where supported through a MMIO
// interface.
BaseTLB::Mode tlb_mode(write ? BaseTLB::Write : BaseTLB::Read);
- Fault fault(tc->getDTBPtr()->finalizePhysical(mmio_req, tc, tlb_mode));
+ Fault fault(tc->getMMUPtr()->finalizePhysical(mmio_req, tc, tlb_mode));
if (fault != NoFault)
warn("Finalization of MMIO address failed: %s\n", fault->name());
diff --git a/src/cpu/minor/cpu.cc b/src/cpu/minor/cpu.cc
index a375e07..c8abfdf 100644
--- a/src/cpu/minor/cpu.cc
+++ b/src/cpu/minor/cpu.cc
@@ -55,11 +55,11 @@
for (ThreadID i = 0; i < numThreads; i++) {
if (FullSystem) {
thread = new Minor::MinorThread(this, i, params->system,
- params->itb, params->dtb, params->isa[i]);
+ params->mmu, params->isa[i]);
thread->setStatus(ThreadContext::Halted);
} else {
thread = new Minor::MinorThread(this, i, params->system,
- params->workload[i], params->itb, params->dtb,
+ params->workload[i], params->mmu,
params->isa[i]);
}
diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh
index 58301a0..83a2e69 100644
--- a/src/cpu/minor/exec_context.hh
+++ b/src/cpu/minor/exec_context.hh
@@ -432,8 +432,7 @@
void
demapPage(Addr vaddr, uint64_t asn) override
{
- thread.getITBPtr()->demapPage(vaddr, asn);
- thread.getDTBPtr()->demapPage(vaddr, asn);
+ thread.getMMUPtr()->demapPage(vaddr, asn);
}
RegVal
@@ -468,17 +467,29 @@
public:
// monitor/mwait funtions
- void armMonitor(Addr address) override
- { getCpuPtr()->armMonitor(inst->id.threadId, address); }
+ void
+ armMonitor(Addr address) override
+ {
+ getCpuPtr()->armMonitor(inst->id.threadId, address);
+ }
- bool mwait(PacketPtr pkt) override
- { return getCpuPtr()->mwait(inst->id.threadId, pkt); }
+ bool
+ mwait(PacketPtr pkt) override
+ {
+ return getCpuPtr()->mwait(inst->id.threadId, pkt);
+ }
- void mwaitAtomic(ThreadContext *tc) override
- { return getCpuPtr()->mwaitAtomic(inst->id.threadId, tc, thread.dtb); }
+ void
+ mwaitAtomic(ThreadContext *tc) override
+ {
+ return getCpuPtr()->mwaitAtomic(inst->id.threadId, tc, thread.mmu);
+ }
- AddressMonitor *getAddrMonitor() override
- { return getCpuPtr()->getCpuAddrMonitor(inst->id.threadId); }
+ AddressMonitor *
+ getAddrMonitor() override
+ {
+ return getCpuPtr()->getCpuAddrMonitor(inst->id.threadId);
+ }
};
}
diff --git a/src/cpu/minor/fetch1.cc b/src/cpu/minor/fetch1.cc
index 4977e3d..00e68e2 100644
--- a/src/cpu/minor/fetch1.cc
+++ b/src/cpu/minor/fetch1.cc
@@ -184,7 +184,7 @@
/* Submit the translation request. The response will come
* through finish/markDelayed on this request as it bears
* the Translation interface */
- cpu.threads[request->id.threadId]->itb->translateTiming(
+ cpu.threads[request->id.threadId]->mmu->translateTiming(
request->request,
cpu.getContext(request->id.threadId),
request, BaseTLB::Execute);
diff --git a/src/cpu/minor/lsq.cc b/src/cpu/minor/lsq.cc
index d8c1c7a..5ae0c1e 100644
--- a/src/cpu/minor/lsq.cc
+++ b/src/cpu/minor/lsq.cc
@@ -311,7 +311,7 @@
/* Submit the translation request. The response will come through
* finish/markDelayed on the LSQRequest as it bears the
Translation
* interface */
- thread->getDTBPtr()->translateTiming(
+ thread->getMMUPtr()->translateTiming(
request, thread, this, (isLoad ? BaseTLB::Read :
BaseTLB::Write));
} else {
disableMemAccess();
@@ -714,7 +714,7 @@
port.numAccessesInDTLB++;
numInTranslationFragments++;
- thread->getDTBPtr()->translateTiming(
+ thread->getMMUPtr()->translateTiming(
fragmentRequests[fragment_index], thread, this, (isLoad ?
BaseTLB::Read : BaseTLB::Write));
}
diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py
index 51d9121..087dbb0 100644
--- a/src/cpu/o3/O3CPU.py
+++ b/src/cpu/o3/O3CPU.py
@@ -179,14 +179,15 @@
def addCheckerCpu(self):
if buildEnv['TARGET_ISA'] in ['arm']:
- from m5.objects.ArmTLB import ArmDTB, ArmITB
+ from m5.objects.ArmTLB import ArmMMU
self.checker = O3Checker(workload=self.workload,
exitOnError=False,
updateOnError=True,
warnOnlyOnLoadError=True)
- self.checker.itb = ArmITB(size = self.itb.size)
- self.checker.dtb = ArmDTB(size = self.dtb.size)
+ self.checker.mmu = ArmMMU()
+ self.checker.mmu.itb.size = self.mmu.itb.size
+ self.checker.mmu.dtb.size = self.mmu.dtb.size
self.checker.cpu_id = self.cpu_id
else:
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 11fac25..393cd22 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -81,8 +81,7 @@
template <class Impl>
FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
: BaseO3CPU(params),
- itb(params->itb),
- dtb(params->dtb),
+ mmu(params->mmu),
tickEvent([this]{ tick(); }, "FullO3CPU tick",
false, Event::CPU_Tick_Pri),
threadExitEvent([this]{ exitThreads(); }, "FullO3CPU exit threads",
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 200d343..19a5560 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -119,8 +119,7 @@
SwitchedOut
};
- BaseTLB *itb;
- BaseTLB *dtb;
+ BaseMMU *mmu;
using LSQRequest = typename LSQ<Impl>::LSQRequest;
/** Overall CPU status. */
@@ -194,18 +193,17 @@
void demapPage(Addr vaddr, uint64_t asn)
{
- this->itb->demapPage(vaddr, asn);
- this->dtb->demapPage(vaddr, asn);
+ mmu->demapPage(vaddr, asn);
}
void demapInstPage(Addr vaddr, uint64_t asn)
{
- this->itb->demapPage(vaddr, asn);
+ mmu->itb->demapPage(vaddr, asn);
}
void demapDataPage(Addr vaddr, uint64_t asn)
{
- this->dtb->demapPage(vaddr, asn);
+ mmu->dtb->demapPage(vaddr, asn);
}
/** Ticks CPU, calling tick() on each stage, and checking the overall
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index d38420b..c180adf 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -609,7 +609,7 @@
// Initiate translation of the icache block
fetchStatus[tid] = ItlbWait;
FetchTranslation *trans = new FetchTranslation(this);
- cpu->itb->translateTiming(mem_req, cpu->thread[tid]->getTC(),
+ cpu->mmu->translateTiming(mem_req, cpu->thread[tid]->getTC(),
trans, BaseTLB::Execute);
return true;
}
diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index c4cb45e..6b38e71 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -970,7 +970,7 @@
LSQ<Impl>::LSQRequest::sendFragmentToTranslation(int i)
{
numInTranslationFragments++;
- _port.dTLB()->translateTiming(
+ _port.getMMUPtr()->translateTiming(
this->request(i),
this->_inst->thread->getTC(), this,
this->isLoad() ? BaseTLB::Read : BaseTLB::Write);
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 3d6e3f0..5abf59b 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -401,7 +401,7 @@
/** Schedule event for the cpu. */
void schedule(Event& ev, Tick when) { cpu->schedule(ev, when); }
- BaseTLB* dTLB() { return cpu->dtb; }
+ BaseMMU* getMMUPtr() { return cpu->mmu; }
private:
/** Pointer to the CPU. */
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index 8d6edbf..d4353d1 100644
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -99,10 +99,13 @@
O3ThreadState<Impl> *thread;
/** Returns a pointer to the ITB. */
- BaseTLB *getITBPtr() override { return cpu->itb; }
+ BaseTLB *getITBPtr() override { return cpu->mmu->itb; }
/** Returns a pointer to the DTB. */
- BaseTLB *getDTBPtr() override { return cpu->dtb; }
+ BaseTLB *getDTBPtr() override { return cpu->mmu->dtb; }
+
+ /** Returns a pointer to the MMU. */
+ BaseMMU *getMMUPtr() override { return cpu->mmu; }
CheckerCPU *getCheckerCpuPtr() override { return NULL; }
diff --git a/src/cpu/simple/BaseSimpleCPU.py
b/src/cpu/simple/BaseSimpleCPU.py
index f05a2b1..f60d005 100644
--- a/src/cpu/simple/BaseSimpleCPU.py
+++ b/src/cpu/simple/BaseSimpleCPU.py
@@ -40,11 +40,12 @@
def addCheckerCpu(self):
if buildEnv['TARGET_ISA'] in ['arm']:
- from m5.objects.ArmTLB import ArmITB, ArmDTB
+ from m5.objects.ArmTLB import ArmMMU
self.checker = DummyChecker(workload = self.workload)
- self.checker.itb = ArmITB(size = self.itb.size)
- self.checker.dtb = ArmDTB(size = self.dtb.size)
+ self.checker.mmu = ArmMMU()
+ self.checker.mmu.itb.size = self.mmu.itb.size
+ self.checker.mmu.dtb.size = self.mmu.dtb.size
else:
print("ERROR: Checker only supported under ARM ISA!")
exit(1)
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 20c6e1c..88e1b1b 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -395,7 +395,7 @@
// translate to physical address
if (predicate) {
- fault = thread->dtb->translateAtomic(req, thread->getTC(),
+ fault = thread->mmu->translateAtomic(req, thread->getTC(),
BaseTLB::Read);
}
@@ -486,7 +486,7 @@
// translate to physical address
if (predicate)
- fault = thread->dtb->translateAtomic(req, thread->getTC(),
+ fault = thread->mmu->translateAtomic(req, thread->getTC(),
BaseTLB::Write);
// Now do the access.
@@ -596,8 +596,8 @@
thread->pcState().instAddr(), std::move(amo_op));
// translate to physical address
- Fault fault = thread->dtb->translateAtomic(req, thread->getTC(),
- BaseTLB::Write);
+ Fault fault = thread->mmu->translateAtomic(
+ req, thread->getTC(), BaseTLB::Write);
// Now do the access.
if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
@@ -673,7 +673,7 @@
if (needToFetch) {
ifetch_req->taskId(taskId());
setupFetchRequest(ifetch_req);
- fault = thread->itb->translateAtomic(ifetch_req,
thread->getTC(),
+ fault = thread->mmu->translateAtomic(ifetch_req,
thread->getTC(),
BaseTLB::Execute);
}
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 132d919..22a39c8 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -92,11 +92,11 @@
for (unsigned i = 0; i < numThreads; i++) {
if (FullSystem) {
- thread = new SimpleThread(this, i, p->system,
- p->itb, p->dtb, p->isa[i]);
+ thread = new SimpleThread(
+ this, i, p->system, p->mmu, p->isa[i]);
} else {
- thread = new SimpleThread(this, i, p->system, p->workload[i],
- p->itb, p->dtb, p->isa[i]);
+ thread = new SimpleThread(
+ this, i, p->system, p->workload[i], p->mmu, p->isa[i]);
}
threadInfo.push_back(new SimpleExecContext(this, thread));
ThreadContext *tc = thread->getTC();
diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh
index fbd2d96..3e98f57 100644
--- a/src/cpu/simple/exec_context.hh
+++ b/src/cpu/simple/exec_context.hh
@@ -576,7 +576,7 @@
void
mwaitAtomic(ThreadContext *tc) override
{
- cpu->mwaitAtomic(thread->threadId(), tc, thread->dtb);
+ cpu->mwaitAtomic(thread->threadId(), tc, thread->mmu);
}
AddressMonitor *
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index c898d79..d6a7bda 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -490,14 +490,14 @@
DataTranslation<TimingSimpleCPU *> *trans2 =
new DataTranslation<TimingSimpleCPU *>(this, state, 1);
- thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode);
- thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode);
+ thread->mmu->translateTiming(req1, thread->getTC(), trans1, mode);
+ thread->mmu->translateTiming(req2, thread->getTC(), trans2, mode);
} else {
WholeTranslationState *state =
new WholeTranslationState(req, new uint8_t[size], NULL, mode);
DataTranslation<TimingSimpleCPU *> *translation
= new DataTranslation<TimingSimpleCPU *>(this, state);
- thread->dtb->translateTiming(req, thread->getTC(), translation,
mode);
+ thread->mmu->translateTiming(req, thread->getTC(), translation,
mode);
}
return NoFault;
@@ -577,14 +577,14 @@
DataTranslation<TimingSimpleCPU *> *trans2 =
new DataTranslation<TimingSimpleCPU *>(this, state, 1);
- thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode);
- thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode);
+ thread->mmu->translateTiming(req1, thread->getTC(), trans1, mode);
+ thread->mmu->translateTiming(req2, thread->getTC(), trans2, mode);
} else {
WholeTranslationState *state =
new WholeTranslationState(req, newData, res, mode);
DataTranslation<TimingSimpleCPU *> *translation =
new DataTranslation<TimingSimpleCPU *>(this, state);
- thread->dtb->translateTiming(req, thread->getTC(), translation,
mode);
+ thread->mmu->translateTiming(req, thread->getTC(), translation,
mode);
}
// Translation faults will be returned via finishTranslation()
@@ -634,7 +634,7 @@
new WholeTranslationState(req, new uint8_t[size], NULL, mode);
DataTranslation<TimingSimpleCPU *> *translation
= new DataTranslation<TimingSimpleCPU *>(this, state);
- thread->dtb->translateTiming(req, thread->getTC(), translation, mode);
+ thread->mmu->translateTiming(req, thread->getTC(), translation, mode);
return NoFault;
}
@@ -710,7 +710,7 @@
ifetch_req->setContext(thread->contextId());
setupFetchRequest(ifetch_req);
DPRINTF(SimpleCPU, "Translating address %#x\n",
ifetch_req->getVaddr());
- thread->itb->translateTiming(ifetch_req, thread->getTC(),
+ thread->mmu->translateTiming(ifetch_req, thread->getTC(),
&fetchTranslation, BaseTLB::Execute);
} else {
_status = IcacheWaitResponse;
diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index 28a1c80..1a50ce1 100644
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -66,13 +66,13 @@
// constructor
SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
- Process *_process, BaseTLB *_itb,
- BaseTLB *_dtb, BaseISA *_isa)
+ Process *_process, BaseMMU *_mmu,
+ BaseISA *_isa)
: ThreadState(_cpu, _thread_num, _process),
isa(dynamic_cast<TheISA::ISA *>(_isa)),
predicate(true), memAccPredicate(true),
comInstEventQueue("instruction-based event queue"),
- system(_sys), itb(_itb), dtb(_dtb), decoder(isa),
+ system(_sys), mmu(_mmu), decoder(isa),
htmTransactionStarts(0), htmTransactionStops(0)
{
assert(isa);
@@ -80,12 +80,12 @@
}
SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
- BaseTLB *_itb, BaseTLB *_dtb, BaseISA *_isa)
+ BaseMMU *_mmu, BaseISA *_isa)
: ThreadState(_cpu, _thread_num, NULL),
isa(dynamic_cast<TheISA::ISA *>(_isa)),
predicate(true), memAccPredicate(true),
comInstEventQueue("instruction-based event queue"),
- system(_sys), itb(_itb), dtb(_dtb), decoder(isa),
+ system(_sys), mmu(_mmu), decoder(isa),
htmTransactionStarts(0), htmTransactionStops(0)
{
assert(isa);
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 255140f..142f220 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -130,8 +130,7 @@
System *system;
- BaseTLB *itb;
- BaseTLB *dtb;
+ BaseMMU *mmu;
TheISA::Decoder decoder;
@@ -142,10 +141,10 @@
// constructor: initialize SimpleThread from given process structure
// FS
SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
- BaseTLB *_itb, BaseTLB *_dtb, BaseISA *_isa);
+ BaseMMU *_mmu, BaseISA *_isa);
// SE
SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
- Process *_process, BaseTLB *_itb, BaseTLB *_dtb,
+ Process *_process, BaseMMU *_mmu,
BaseISA *_isa);
virtual ~SimpleThread() {}
@@ -170,18 +169,17 @@
void demapPage(Addr vaddr, uint64_t asn)
{
- itb->demapPage(vaddr, asn);
- dtb->demapPage(vaddr, asn);
+ mmu->demapPage(vaddr, asn);
}
void demapInstPage(Addr vaddr, uint64_t asn)
{
- itb->demapPage(vaddr, asn);
+ mmu->itb->demapPage(vaddr, asn);
}
void demapDataPage(Addr vaddr, uint64_t asn)
{
- dtb->demapPage(vaddr, asn);
+ mmu->dtb->demapPage(vaddr, asn);
}
/*******************************************
@@ -216,9 +214,11 @@
ContextID contextId() const override { return
ThreadState::contextId(); }
void setContextId(ContextID id) override {
ThreadState::setContextId(id); }
- BaseTLB *getITBPtr() override { return itb; }
+ BaseTLB *getITBPtr() override { return mmu->itb; }
- BaseTLB *getDTBPtr() override { return dtb; }
+ BaseTLB *getDTBPtr() override { return mmu->dtb; }
+
+ BaseMMU *getMMUPtr() override { return mmu; }
CheckerCPU *getCheckerCpuPtr() override { return NULL; }
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index a6f7869..9bd5cf5 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -61,6 +61,7 @@
class Decoder;
}
class BaseCPU;
+class BaseMMU;
class BaseTLB;
class CheckerCPU;
class Checkpoint;
@@ -133,6 +134,8 @@
virtual BaseTLB *getDTBPtr() = 0;
+ virtual BaseMMU *getMMUPtr() = 0;
+
virtual CheckerCPU *getCheckerCpuPtr() = 0;
virtual BaseISA *getIsaPtr() = 0;
diff --git a/tests/configs/pc-simple-timing-ruby.py
b/tests/configs/pc-simple-timing-ruby.py
index 06a3efc..a2da8d8 100644
--- a/tests/configs/pc-simple-timing-ruby.py
+++ b/tests/configs/pc-simple-timing-ruby.py
@@ -80,8 +80,8 @@
# Tie the cpu ports to the correct ruby system ports
cpu.icache_port = system.ruby._cpu_ports[i].slave
cpu.dcache_port = system.ruby._cpu_ports[i].slave
- cpu.itb.walker.port = system.ruby._cpu_ports[i].slave
- cpu.dtb.walker.port = system.ruby._cpu_ports[i].slave
+ cpu.mmu.itb.walker.port = system.ruby._cpu_ports[i].slave
+ cpu.mmu.dtb.walker.port = system.ruby._cpu_ports[i].slave
cpu.interrupts[0].pio = system.ruby._cpu_ports[i].master
cpu.interrupts[0].int_master = system.ruby._cpu_ports[i].slave
diff --git a/tests/gem5/x86-boot-tests/system/caches.py
b/tests/gem5/x86-boot-tests/system/caches.py
index 2c2e520..441fba9 100755
--- a/tests/gem5/x86-boot-tests/system/caches.py
+++ b/tests/gem5/x86-boot-tests/system/caches.py
@@ -113,7 +113,7 @@
"""
self.mmubus = L2XBar()
self.cpu_side = self.mmubus.master
- for tlb in [cpu.itb, cpu.dtb]:
+ for tlb in [cpu.mmu.itb, cpu.mmu.dtb]:
self.mmubus.slave = tlb.walker.port
def connectBus(self, bus):
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4932a32f68582b25cd252b5420b54d6a40ee15b8
Gerrit-Change-Number: 34976
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@gmail.com>
Gerrit-MessageType: newchange
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