Pouya Fotouhi has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/32317 )
Change subject: mem-ruby: Adding FS support for MOESI_AMD_Base
......................................................................
mem-ruby: Adding FS support for MOESI_AMD_Base
WIP
Change-Id: Ic424cc6e78399e9cd73d6419ea0ad6f8c9397673
---
M configs/ruby/MOESI_AMD_Base.py
M src/mem/ruby/protocol/MOESI_AMD_Base.slicc
2 files changed, 56 insertions(+), 3 deletions(-)
diff --git a/configs/ruby/MOESI_AMD_Base.py b/configs/ruby/MOESI_AMD_Base.py
index 91ff4d2..ae17031 100644
--- a/configs/ruby/MOESI_AMD_Base.py
+++ b/configs/ruby/MOESI_AMD_Base.py
@@ -260,6 +260,12 @@
dir_cntrl.create(options, dir_ranges, ruby_system, system)
# Connect the Directory controller to the ruby network
+ dir_cntrl.requestFromDMA = MessageBuffer(ordered = True)
+ dir_cntrl.requestFromDMA.slave = ruby_system.network.master
+
+ dir_cntrl.responseToDMA = MessageBuffer()
+ dir_cntrl.responseToDMA.master = ruby_system.network.slave
+
dir_cntrl.requestFromCores = MessageBuffer(ordered = True)
dir_cntrl.requestFromCores.slave = ruby_system.network.master
@@ -290,7 +296,7 @@
# level config files, such as the ruby_random_tester, will get
confused if
# the number of cpus does not equal the number of sequencers. Thus
make
# sure that an even number of cpus is specified.
- assert((options.num_cpus % 2) == 0)
+# assert((options.num_cpus % 2) == 0)
# For an odd number of CPUs, still create the right number of
controllers
cpuCluster = Cluster(extBW = 512, intBW = 512) # 1 TB/s
@@ -378,8 +384,54 @@
cpus = [n for n in
range(options.num_cpus)])
- # Assuming no DMA devices
- assert(len(dma_devices) == 0)
+## # Assuming no DMA devices
+## assert(len(dma_devices) == 0)
+## dma_cntrl_nodes = []
+
+ for i, dma_port in enumerate(dma_devices):
+ # Create the Ruby objects associated with the dma controller
+ dma_seq = DMASequencer(version = i, ruby_system = ruby_system,
+ slave = dma_port)
+
+ dma_cntrl = DMA_Controller(version = i, dma_sequencer = dma_seq,
+ transitions_per_cycle = options.ports,
+ ruby_system = ruby_system)
+
+ exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
+# dma_cntrl_nodes.append(dma_cntrl)
+
+ # Connect the dma controller to the network
+ dma_cntrl.mandatoryQueue = MessageBuffer()
+ dma_cntrl.responseFromDir = MessageBuffer(ordered = True)
+ dma_cntrl.responseFromDir.slave = ruby_system.network.master
+ dma_cntrl.requestToDir = MessageBuffer()
+ dma_cntrl.requestToDir.master = ruby_system.network.slave
+
+ mainCluster.add(dma_cntrl)
+
+ # Create the io controller and the sequencer
+ if full_system:
+ io_seq = DMASequencer(version = len(dma_devices),
+ ruby_system = ruby_system)
+ ruby_system._io_port = io_seq
+ io_controller = DMA_Controller(version = len(dma_devices),
+ dma_sequencer = io_seq,
+ ruby_system = ruby_system)
+ ruby_system.io_controller = io_controller
+
+ # Connect the dma controller to the network
+ io_controller.mandatoryQueue = MessageBuffer()
+ io_controller.responseFromDir = MessageBuffer(ordered = True)
+ io_controller.responseFromDir.slave = ruby_system.network.master
+ io_controller.requestToDir = MessageBuffer()
+ io_controller.requestToDir.master = ruby_system.network.slave
+
+ #dma_cntrl_nodes.append(io_controller)
+ mainCluster.add(io_controller)
+
+
+# mainCluster.add(dma_cntrl_nodes)
+
# Add cpu/gpu clusters to main cluster
mainCluster.add(cpuCluster)
diff --git a/src/mem/ruby/protocol/MOESI_AMD_Base.slicc
b/src/mem/ruby/protocol/MOESI_AMD_Base.slicc
index b381452..dd4b0fc 100644
--- a/src/mem/ruby/protocol/MOESI_AMD_Base.slicc
+++ b/src/mem/ruby/protocol/MOESI_AMD_Base.slicc
@@ -4,3 +4,4 @@
include "MOESI_AMD_Base-CorePair.sm";
include "MOESI_AMD_Base-L3cache.sm";
include "MOESI_AMD_Base-dir.sm";
+include "MOESI_AMD_Base-dma.sm";
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic424cc6e78399e9cd73d6419ea0ad6f8c9397673
Gerrit-Change-Number: 32317
Gerrit-PatchSet: 1
Gerrit-Owner: Pouya Fotouhi <pfoto...@ucdavis.edu>
Gerrit-MessageType: newchange
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