Matthew Poremba has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56448 )
Change subject: mem-ruby: Support partial DMA/memory writes
......................................................................
mem-ruby: Support partial DMA/memory writes
Partial cache line requests are requests to memory which are less than
the size of a cache line. These are used heavily in DMA requests from
the GPU model but the current support forces the address to align with
the cache line address, which eventually requests in the wrong data
being selected from the request.
This adds support by passing along the byte address of the request from
the directory to AbstractController. The AbstractController creates a
packet using the byte address rather than the line address. The line
address is restored before responding to SLICC code which operates on
line addresses.
Change-Id: I9827441a4c07a8e01d12b2e9b84880ab77f91002
JIRA: https://gem5.atlassian.net/browse/GEM5-564
---
M src/mem/ruby/protocol/RubySlicc_MemControl.sm
M src/mem/ruby/slicc_interface/AbstractController.cc
2 files changed, 30 insertions(+), 5 deletions(-)
diff --git a/src/mem/ruby/protocol/RubySlicc_MemControl.sm
b/src/mem/ruby/protocol/RubySlicc_MemControl.sm
index e8517a4..e642769 100644
--- a/src/mem/ruby/protocol/RubySlicc_MemControl.sm
+++ b/src/mem/ruby/protocol/RubySlicc_MemControl.sm
@@ -63,7 +63,8 @@
// Message to and from Memory Control
structure(MemoryMsg, desc="...", interface="Message") {
- Addr addr, desc="Physical address for this request";
+ Addr addr, desc="Cache line address for this request";
+ Addr ByteAddr, default="0", desc="Byte address for this request";
MemoryRequestType Type, desc="Type of memory request (MEMORY_READ
or MEMORY_WB)";
MachineID Sender, desc="What component sent the data";
MachineID OriginalRequestorMachId, desc="What component originally
requested";
diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc
b/src/mem/ruby/slicc_interface/AbstractController.cc
index 396b128..d9c1507 100644
--- a/src/mem/ruby/slicc_interface/AbstractController.cc
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc
@@ -266,13 +266,15 @@
req_size = mem_msg->m_Len;
}
- RequestPtr req
- = std::make_shared<Request>(mem_msg->m_addr, req_size, 0, m_id);
+ Addr req_addr = mem_msg->m_ByteAddr ? mem_msg->m_ByteAddr
+ : mem_msg->m_addr;
+
+ RequestPtr req = std::make_shared<Request>(req_addr, req_size, 0,
m_id);
PacketPtr pkt;
if (mem_msg->getType() == MemoryRequestType_MEMORY_WB) {
pkt = Packet::createWrite(req);
pkt->allocate();
- pkt->setData(mem_msg->m_DataBlk.getData(getOffset(mem_msg->m_addr),
+ pkt->setData(mem_msg->m_DataBlk.getData(getOffset(req_addr),
req_size));
} else if (mem_msg->getType() == MemoryRequestType_MEMORY_READ) {
pkt = Packet::createRead(req);
@@ -370,7 +372,7 @@
assert(pkt->isResponse());
std::shared_ptr<MemoryMsg> msg =
std::make_shared<MemoryMsg>(clockEdge());
- (*msg).m_addr = pkt->getAddr();
+ (*msg).m_addr = makeLineAddress(pkt->getAddr());
(*msg).m_Sender = m_machineID;
SenderState *s = dynamic_cast<SenderState *>(pkt->senderState);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9827441a4c07a8e01d12b2e9b84880ab77f91002
Gerrit-Change-Number: 56448
Gerrit-PatchSet: 1
Gerrit-Owner: Matthew Poremba <matthew.pore...@amd.com>
Gerrit-MessageType: newchange
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