Jason Lowe-Power has uploaded this change for review. (
https://gem5-review.googlesource.com/8962
Change subject: arch-x86: Serialize TSC reads
......................................................................
arch-x86: Serialize TSC reads
When reading the timestamp counter (rdtsc and rdtscp) all previous
instructions should be committed. Make reading the TscOp serialize
Before to force this to be true.
Change-Id: If81e22c643b46cf7ac08f6f1b13f16d83ffcae63
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
---
M src/arch/x86/isa/operands.isa
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index de7ee5a..c195995 100644
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -67,11 +67,10 @@
return ('FloatReg', 'df', idx, 'IsFloating', id)
def ccReg(idx, id):
return ('CCReg', 'uqw', idx, 'IsCC', id)
- def controlReg(idx, id, ctype = 'uqw'):
+ def controlReg(idx, id, ctype = 'uqw', read_serial=False):
return ('ControlReg', ctype, idx,
- (None, None, ['IsSerializeAfter',
- 'IsSerializing',
- 'IsNonSpeculative']),
+ (None, ['IsSerializeBefore'] if read_serial else None,
+
['IsSerializeAfter', 'IsSerializing', 'IsNonSpeculative']),
id)
def squashCheckReg(idx, id, check, ctype = 'uqw'):
return ('ControlReg', ctype, idx,
@@ -204,7 +203,7 @@
'CSAttr': squashCReg('MISCREG_CS_ATTR', 209),
'MiscRegDest': controlReg('dest', 210),
'MiscRegSrc1': controlReg('src1', 211),
- 'TscOp': controlReg('MISCREG_TSC', 212),
+ 'TscOp': controlReg('MISCREG_TSC', 212, read_serial=True),
'M5Reg': squashCReg('MISCREG_M5_REG', 213),
'Mem': ('Mem', 'uqw', None, \
('IsMemRef', 'IsLoad', 'IsStore'), 300)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: master
Gerrit-Change-Id: If81e22c643b46cf7ac08f6f1b13f16d83ffcae63
Gerrit-Change-Number: 8962
Gerrit-PatchSet: 1
Gerrit-Owner: Jason Lowe-Power <ja...@lowepower.com>
Gerrit-MessageType: newchange
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