Hello, I'm trying to add an ISA to gem5 which has several atomic read-modify-write instructions. Currently I have them implemented as pairs of micro-ops which read data in the first operation and then modify-write in the second. This works for the simple CPU model, but runs into trouble for the minor and O3 models, which want to execute the modify-write half before the load half is complete. I tried forcing both parts of the instruction to have the same src and dest register indices, but that causes other problems with the O3 model.
Is there a way to indicate that there is a data dependency between the two micro-ops in the instruction? Or, better yet, is there a way I could somehow have two memory accesses in one instruction without having to split it into micro-ops? Thanks, Alec Roelke _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
