; Giacomo
>
>
>
> *From:* Jason Lowe-Power via gem5-dev
> *Sent:* 21 September 2020 16:02
> *To:* gem5 Developer List
> *Cc:* Jason Lowe-Power
> *Subject:* [gem5-dev] Re: MMU object vs. DTB and ITB
>
>
>
> We (well, mostly Ayaz) have also been looking at
September 2020 16:02
To: gem5 Developer List
Cc: Jason Lowe-Power
Subject: [gem5-dev] Re: MMU object vs. DTB and ITB
We (well, mostly Ayaz) have also been looking at this interface. We've been
thinking more about x86 and RISC-V, but would also like to be kept up to date!
We were also thi
* Gabe Black via gem5-dev
>> *Sent:* 20 September 2020 04:44
>> *To:* gem5 Developer List
>> *Cc:* Gabe Black
>> *Subject:* [gem5-dev] Re: MMU object vs. DTB and ITB
>>
>>
>>
>> Oh, this will also absorb multilevel TLBs too, like how ARM has sec
about to post the same patchset (which is:
> removing the TLB from the CPU interface and make it interface with an MMU
> instead)
>
>
>
> Giacomo
>
>
>
> *From:* Gabe Black via gem5-dev
> *Sent:* 20 September 2020 04:44
> *To:* gem5 Developer List
> *Cc:* Gabe
Hi Gabe, I am actually about to post the same patchset (which is: removing the
TLB from the CPU interface and make it interface with an MMU instead)
Giacomo
From: Gabe Black via gem5-dev
Sent: 20 September 2020 04:44
To: gem5 Developer List
Cc: Gabe Black
Subject: [gem5-dev] Re: MMU object
Oh, this will also absorb multilevel TLBs too, like how ARM has second
level translation in some cases. This isn't really implemented in x86, but
could also be used for it's multilevel translation in SVM and VT's nested
page table schemes.
Gabe
On Sat, Sep 19, 2020 at 8:25 PM Gabe Black wrote:
