changeset 25c5da51bbe0 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=25c5da51bbe0 description: arm: Add TLB PMU probes
This changeset adds probe points that can be used to implement PMU counters for TLB stats. The following probes are supported: * ArmISA::TLB::ppRefills / TLB Refills (TLB insertions) diffstat: src/arch/arm/tlb.cc | 7 +++++++ src/arch/arm/tlb.hh | 6 ++++++ 2 files changed, 13 insertions(+), 0 deletions(-) diffs (54 lines): diff -r e975e8afba8b -r 25c5da51bbe0 src/arch/arm/tlb.cc --- a/src/arch/arm/tlb.cc Thu Oct 16 05:49:40 2014 -0400 +++ b/src/arch/arm/tlb.cc Thu Oct 16 05:49:41 2014 -0400 @@ -197,6 +197,7 @@ table[0] = entry; inserts++; + ppRefills->notify(1); } void @@ -531,6 +532,12 @@ accesses = readAccesses + writeAccesses + instAccesses; } +void +TLB::regProbePoints() +{ + ppRefills.reset(new ProbePoints::PMU(getProbeManager(), "Refills")); +} + Fault TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode, Translation *translation, bool &delay, bool timing) diff -r e975e8afba8b -r 25c5da51bbe0 src/arch/arm/tlb.hh --- a/src/arch/arm/tlb.hh Thu Oct 16 05:49:40 2014 -0400 +++ b/src/arch/arm/tlb.hh Thu Oct 16 05:49:41 2014 -0400 @@ -53,6 +53,7 @@ #include "mem/request.hh" #include "params/ArmTLB.hh" #include "sim/fault_fwd.hh" +#include "sim/probe/pmu.hh" #include "sim/tlb.hh" class ThreadContext; @@ -131,6 +132,9 @@ Stats::Formula misses; Stats::Formula accesses; + /** PMU probe for TLB refills */ + ProbePoints::PMUUPtr ppRefills; + int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU bool bootUncacheability; @@ -291,6 +295,8 @@ void regStats(); + void regProbePoints() M5_ATTR_OVERRIDE; + /** * Get the table walker master port. This is used for migrating * port connections during a CPU takeOverFrom() call. For _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev