changeset f5ceb3c3edb6 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=f5ceb3c3edb6
description:
config: ruby: rename _cpu_ruby_ports to _cpu_ports
diffstat:
configs/example/fs.py | 16 ++++++++--------
configs/example/ruby_direct_test.py | 4 ++--
configs/example/ruby_mem_test.py | 8 ++++----
configs/example/ruby_network_test.py | 2 +-
configs/example/ruby_random_test.py | 6 +++---
configs/example/se.py | 4 ++--
configs/ruby/Ruby.py | 2 +-
tests/configs/memtest-ruby.py | 4 ++--
tests/configs/pc-simple-timing-ruby.py | 16 ++++++++--------
tests/configs/rubytest-ruby.py | 4 ++--
tests/configs/simple-timing-mp-ruby.py | 4 ++--
tests/configs/simple-timing-ruby.py | 4 ++--
12 files changed, 37 insertions(+), 37 deletions(-)
diffs (248 lines):
diff -r 6f3f839bb496 -r f5ceb3c3edb6 configs/example/fs.py
--- a/configs/example/fs.py Thu Mar 20 09:14:08 2014 -0500
+++ b/configs/example/fs.py Thu Mar 20 09:14:14 2014 -0500
@@ -149,18 +149,18 @@
cpu.createThreads()
cpu.createInterruptController()
- cpu.icache_port = test_sys.ruby._cpu_ruby_ports[i].slave
- cpu.dcache_port = test_sys.ruby._cpu_ruby_ports[i].slave
+ cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
+ cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
if buildEnv['TARGET_ISA'] == "x86":
- cpu.itb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave
- cpu.dtb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave
+ cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
+ cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
- cpu.interrupts.pio = test_sys.ruby._cpu_ruby_ports[i].master
- cpu.interrupts.int_master =
test_sys.ruby._cpu_ruby_ports[i].slave
- cpu.interrupts.int_slave =
test_sys.ruby._cpu_ruby_ports[i].master
+ cpu.interrupts.pio = test_sys.ruby._cpu_ports[i].master
+ cpu.interrupts.int_master = test_sys.ruby._cpu_ports[i].slave
+ cpu.interrupts.int_slave = test_sys.ruby._cpu_ports[i].master
- test_sys.ruby._cpu_ruby_ports[i].access_phys_mem = True
+ test_sys.ruby._cpu_ports[i].access_phys_mem = True
# Create the appropriate memory controllers
# and connect them to the IO bus
diff -r 6f3f839bb496 -r f5ceb3c3edb6 configs/example/ruby_direct_test.py
--- a/configs/example/ruby_direct_test.py Thu Mar 20 09:14:08 2014 -0500
+++ b/configs/example/ruby_direct_test.py Thu Mar 20 09:14:14 2014 -0500
@@ -115,9 +115,9 @@
system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
voltage_domain = system.voltage_domain)
-assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
+assert(options.num_cpus == len(system.ruby._cpu_ports))
-for ruby_port in system.ruby._cpu_ruby_ports:
+for ruby_port in system.ruby._cpu_ports:
#
# Tie the ruby tester ports to the ruby cpu ports
#
diff -r 6f3f839bb496 -r f5ceb3c3edb6 configs/example/ruby_mem_test.py
--- a/configs/example/ruby_mem_test.py Thu Mar 20 09:14:08 2014 -0500
+++ b/configs/example/ruby_mem_test.py Thu Mar 20 09:14:14 2014 -0500
@@ -144,26 +144,26 @@
#
system.ruby.randomization = True
-assert(len(cpus) == len(system.ruby._cpu_ruby_ports))
+assert(len(cpus) == len(system.ruby._cpu_ports))
for (i, cpu) in enumerate(cpus):
#
# Tie the cpu memtester ports to the correct system ports
#
- cpu.test = system.ruby._cpu_ruby_ports[i].slave
+ cpu.test = system.ruby._cpu_ports[i].slave
cpu.functional = system.funcbus.slave
#
# Since the memtester is incredibly bursty, increase the deadlock
# threshold to 5 million cycles
#
- system.ruby._cpu_ruby_ports[i].deadlock_threshold = 5000000
+ system.ruby._cpu_ports[i].deadlock_threshold = 5000000
#
# Ruby doesn't need the backing image of memory when running with
# the tester.
#
- system.ruby._cpu_ruby_ports[i].access_phys_mem = False
+ system.ruby._cpu_ports[i].access_phys_mem = False
for (i, dma) in enumerate(dmas):
#
diff -r 6f3f839bb496 -r f5ceb3c3edb6 configs/example/ruby_network_test.py
--- a/configs/example/ruby_network_test.py Thu Mar 20 09:14:08 2014 -0500
+++ b/configs/example/ruby_network_test.py Thu Mar 20 09:14:14 2014 -0500
@@ -120,7 +120,7 @@
voltage_domain = system.voltage_domain)
i = 0
-for ruby_port in system.ruby._cpu_ruby_ports:
+for ruby_port in system.ruby._cpu_ports:
#
# Tie the cpu test ports to the ruby cpu port
#
diff -r 6f3f839bb496 -r f5ceb3c3edb6 configs/example/ruby_random_test.py
--- a/configs/example/ruby_random_test.py Thu Mar 20 09:14:08 2014 -0500
+++ b/configs/example/ruby_random_test.py Thu Mar 20 09:14:14 2014 -0500
@@ -112,9 +112,9 @@
system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
voltage_domain = system.voltage_domain)
-assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
+assert(options.num_cpus == len(system.ruby._cpu_ports))
-tester.num_cpus = len(system.ruby._cpu_ruby_ports)
+tester.num_cpus = len(system.ruby._cpu_ports)
#
# The tester is most effective when randomization is turned on and
@@ -122,7 +122,7 @@
#
system.ruby.randomization = True
-for ruby_port in system.ruby._cpu_ruby_ports:
+for ruby_port in system.ruby._cpu_ports:
#
# Tie the ruby tester ports to the ruby cpu read and write ports
#
diff -r 6f3f839bb496 -r f5ceb3c3edb6 configs/example/se.py
--- a/configs/example/se.py Thu Mar 20 09:14:08 2014 -0500
+++ b/configs/example/se.py Thu Mar 20 09:14:14 2014 -0500
@@ -233,10 +233,10 @@
null = True)
options.use_map = True
Ruby.create_system(options, system)
- assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
+ assert(options.num_cpus == len(system.ruby._cpu_ports))
for i in xrange(np):
- ruby_port = system.ruby._cpu_ruby_ports[i]
+ ruby_port = system.ruby._cpu_ports[i]
# Create the interrupt controller and connect its ports to Ruby
# Note that the interrupt controller is always present but only
diff -r 6f3f839bb496 -r f5ceb3c3edb6 configs/ruby/Ruby.py
--- a/configs/ruby/Ruby.py Thu Mar 20 09:14:08 2014 -0500
+++ b/configs/ruby/Ruby.py Thu Mar 20 09:14:14 2014 -0500
@@ -200,6 +200,6 @@
if buildEnv['TARGET_ISA'] == "x86":
cpu_seq.pio_slave_port = piobus.master
- ruby._cpu_ruby_ports = cpu_sequencers
+ ruby._cpu_ports = cpu_sequencers
ruby.num_of_sequencers = len(cpu_sequencers)
ruby.random_seed = options.random_seed
diff -r 6f3f839bb496 -r f5ceb3c3edb6 tests/configs/memtest-ruby.py
--- a/tests/configs/memtest-ruby.py Thu Mar 20 09:14:08 2014 -0500
+++ b/tests/configs/memtest-ruby.py Thu Mar 20 09:14:14 2014 -0500
@@ -104,9 +104,9 @@
system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
voltage_domain = system.voltage_domain)
-assert(len(cpus) == len(system.ruby._cpu_ruby_ports))
+assert(len(cpus) == len(system.ruby._cpu_ports))
-for (i, ruby_port) in enumerate(system.ruby._cpu_ruby_ports):
+for (i, ruby_port) in enumerate(system.ruby._cpu_ports):
#
# Tie the cpu test and functional ports to the ruby cpu ports and
# physmem, respectively
diff -r 6f3f839bb496 -r f5ceb3c3edb6 tests/configs/pc-simple-timing-ruby.py
--- a/tests/configs/pc-simple-timing-ruby.py Thu Mar 20 09:14:08 2014 -0500
+++ b/tests/configs/pc-simple-timing-ruby.py Thu Mar 20 09:14:14 2014 -0500
@@ -78,16 +78,16 @@
# create the interrupt controller
cpu.createInterruptController()
# Tie the cpu ports to the correct ruby system ports
- cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave
- cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave
- cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].slave
- cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].slave
- cpu.interrupts.pio = system.ruby._cpu_ruby_ports[i].master
- cpu.interrupts.int_master = system.ruby._cpu_ruby_ports[i].slave
- cpu.interrupts.int_slave = system.ruby._cpu_ruby_ports[i].master
+ cpu.icache_port = system.ruby._cpu_ports[i].slave
+ cpu.dcache_port = system.ruby._cpu_ports[i].slave
+ cpu.itb.walker.port = system.ruby._cpu_ports[i].slave
+ cpu.dtb.walker.port = system.ruby._cpu_ports[i].slave
+ cpu.interrupts.pio = system.ruby._cpu_ports[i].master
+ cpu.interrupts.int_master = system.ruby._cpu_ports[i].slave
+ cpu.interrupts.int_slave = system.ruby._cpu_ports[i].master
# Set access_phys_mem to True for ruby port
- system.ruby._cpu_ruby_ports[i].access_phys_mem = True
+ system.ruby._cpu_ports[i].access_phys_mem = True
system.physmem = [DDR3_1600_x64(range = r)
for r in system.mem_ranges]
diff -r 6f3f839bb496 -r f5ceb3c3edb6 tests/configs/rubytest-ruby.py
--- a/tests/configs/rubytest-ruby.py Thu Mar 20 09:14:08 2014 -0500
+++ b/tests/configs/rubytest-ruby.py Thu Mar 20 09:14:14 2014 -0500
@@ -92,7 +92,7 @@
system.ruby.clk_domain = SrcClockDomain(clock = '1GHz',
voltage_domain = system.voltage_domain)
-assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
+assert(options.num_cpus == len(system.ruby._cpu_ports))
#
# The tester is most effective when randomization is turned on and
@@ -100,7 +100,7 @@
#
system.ruby.randomization = True
-for ruby_port in system.ruby._cpu_ruby_ports:
+for ruby_port in system.ruby._cpu_ports:
#
# Tie the ruby tester ports to the ruby cpu read and write ports
#
diff -r 6f3f839bb496 -r f5ceb3c3edb6 tests/configs/simple-timing-mp-ruby.py
--- a/tests/configs/simple-timing-mp-ruby.py Thu Mar 20 09:14:08 2014 -0500
+++ b/tests/configs/simple-timing-mp-ruby.py Thu Mar 20 09:14:14 2014 -0500
@@ -83,7 +83,7 @@
# Create a separate clock domain for Ruby
system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
-assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
+assert(options.num_cpus == len(system.ruby._cpu_ports))
for (i, cpu) in enumerate(system.cpu):
# create the interrupt controller
@@ -92,7 +92,7 @@
#
# Tie the cpu ports to the ruby cpu ports
#
- cpu.connectAllPorts(system.ruby._cpu_ruby_ports[i])
+ cpu.connectAllPorts(system.ruby._cpu_ports[i])
# -----------------------
# run simulation
diff -r 6f3f839bb496 -r f5ceb3c3edb6 tests/configs/simple-timing-ruby.py
--- a/tests/configs/simple-timing-ruby.py Thu Mar 20 09:14:08 2014 -0500
+++ b/tests/configs/simple-timing-ruby.py Thu Mar 20 09:14:14 2014 -0500
@@ -85,7 +85,7 @@
system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
voltage_domain = system.voltage_domain)
-assert(len(system.ruby._cpu_ruby_ports) == 1)
+assert(len(system.ruby._cpu_ports) == 1)
# create the interrupt controller
cpu.createInterruptController()
@@ -94,7 +94,7 @@
# Tie the cpu cache ports to the ruby cpu ports and
# physmem, respectively
#
-cpu.connectAllPorts(system.ruby._cpu_ruby_ports[0])
+cpu.connectAllPorts(system.ruby._cpu_ports[0])
# -----------------------
# run simulation
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