changeset 9a34e28cd2c2 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=9a34e28cd2c2
description:
        mem: Ignore uncacheable MSHRs when finding matches

        This patch changes how we search for matching MSHRs, ignoring any MSHR
        that is allocated for an uncacheable access. By doing so, this patch
        fixes a corner case in the MSHRs where incorrect data ended up being
        copied into a (cacheable) read packet due to a first uncacheable MSHR
        target of size 4, followed by a cacheable target to the same MSHR of
        size 64. The latter target was filled with nonsense data.

diffstat:

 src/mem/cache/mshr.cc       |  14 +++++++++-----
 src/mem/cache/mshr_queue.cc |  11 +++++++++--
 2 files changed, 18 insertions(+), 7 deletions(-)

diffs (59 lines):

diff -r 993c2baa485a -r 9a34e28cd2c2 src/mem/cache/mshr.cc
--- a/src/mem/cache/mshr.cc     Fri Mar 27 04:55:59 2015 -0400
+++ b/src/mem/cache/mshr.cc     Fri Mar 27 04:56:00 2015 -0400
@@ -273,6 +273,15 @@
 void
 MSHR::allocateTarget(PacketPtr pkt, Tick whenReady, Counter _order)
 {
+    // assume we'd never issue a prefetch when we've got an
+    // outstanding miss
+    assert(pkt->cmd != MemCmd::HardPFReq);
+
+    // uncacheable accesses always allocate a new MSHR, and cacheable
+    // accesses ignore any uncacheable MSHRs, thus we should never
+    // have targets addded if originally allocated uncacheable
+    assert(!_isUncacheable);
+
     // if there's a request already in service for this MSHR, we will
     // have to defer the new target until after the response if any of
     // the following are true:
@@ -283,11 +292,6 @@
     //   getting an exclusive block back or we have already snooped
     //   another read request that will downgrade our exclusive block
     //   to shared
-
-    // assume we'd never issue a prefetch when we've got an
-    // outstanding miss
-    assert(pkt->cmd != MemCmd::HardPFReq);
-
     if (inService &&
         (!deferredTargets.empty() || hasPostInvalidate() ||
          (pkt->needsExclusive() &&
diff -r 993c2baa485a -r 9a34e28cd2c2 src/mem/cache/mshr_queue.cc
--- a/src/mem/cache/mshr_queue.cc       Fri Mar 27 04:55:59 2015 -0400
+++ b/src/mem/cache/mshr_queue.cc       Fri Mar 27 04:56:00 2015 -0400
@@ -69,7 +69,13 @@
 MSHRQueue::findMatch(Addr blk_addr, bool is_secure) const
 {
     for (const auto& mshr : allocatedList) {
-        if (mshr->blkAddr == blk_addr && mshr->isSecure == is_secure) {
+        // we ignore any MSHRs allocated for uncacheable accesses and
+        // simply ignore them when matching, in the cache we never
+        // check for matches when adding new uncacheable entries, and
+        // we do not want normal cacheable accesses being added to an
+        // MSHR serving an uncacheable access
+        if (!mshr->isUncacheable() && mshr->blkAddr == blk_addr &&
+            mshr->isSecure == is_secure) {
             return mshr;
         }
     }
@@ -84,7 +90,8 @@
     assert(matches.empty());
     bool retval = false;
     for (const auto& mshr : allocatedList) {
-        if (mshr->blkAddr == blk_addr && mshr->isSecure == is_secure) {
+        if (!mshr->isUncacheable() && mshr->blkAddr == blk_addr &&
+            mshr->isSecure == is_secure) {
             retval = true;
             matches.push_back(mshr);
         }
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